diff options
| author | Stefan Weil <sw@weilnetz.de> | 2011-10-09 08:50:50 +0200 |
|---|---|---|
| committer | Blue Swirl <blauwirbel@gmail.com> | 2011-10-09 08:18:30 +0000 |
| commit | 02d6516c8ba00bdd6d96b622f000cb28c3449f43 (patch) | |
| tree | cd7669f42d2a320776d57c7254163d8bf0737620 /hw/alpha_typhoon.c | |
| parent | 9a7242f7867e1f1e70013aa70d148c65a1980aec (diff) | |
target-alpha: Fix compilation errors for 32 bit hosts
On i386, these errors were reported:
qemu/hw/alpha_dp264.c: In function ‘clipper_init’:
qemu/hw/alpha_dp264.c:158: error: integer constant is too large for ‘unsigned long’ type
qemu/hw/alpha_typhoon.c: In function ‘typhoon_init’:
qemu/hw/alpha_typhoon.c:737: error: integer constant is too large for ‘long’ type
qemu/hw/alpha_typhoon.c:741: error: integer constant is too large for ‘long’ type
qemu/hw/alpha_typhoon.c:745: error: integer constant is too large for ‘long’ type
qemu/hw/alpha_typhoon.c:749: error: integer constant is too large for ‘long’ type
qemu/hw/alpha_typhoon.c:757: error: integer constant is too large for ‘long’ type
qemu/hw/alpha_typhoon.c:767: error: integer constant is too large for ‘long’ type
qemu/hw/alpha_typhoon.c:772: error: integer constant is too large for ‘long’ type
Signed-off-by: Stefan Weil <sw@weilnetz.de>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Diffstat (limited to 'hw/alpha_typhoon.c')
| -rw-r--r-- | hw/alpha_typhoon.c | 21 |
1 files changed, 14 insertions, 7 deletions
diff --git a/hw/alpha_typhoon.c b/hw/alpha_typhoon.c index c769fcc138..c7608bbabd 100644 --- a/hw/alpha_typhoon.c +++ b/hw/alpha_typhoon.c @@ -734,19 +734,23 @@ PCIBus *typhoon_init(ram_addr_t ram_size, qemu_irq *p_rtc_irq, /* Pchip0 CSRs, 0x801.8000.0000, 256MB. */ memory_region_init_io(&s->pchip.region, &pchip_ops, s, "pchip0", 256*MB); - memory_region_add_subregion(addr_space, 0x80180000000, &s->pchip.region); + memory_region_add_subregion(addr_space, 0x80180000000ULL, + &s->pchip.region); /* Cchip CSRs, 0x801.A000.0000, 256MB. */ memory_region_init_io(&s->cchip.region, &cchip_ops, s, "cchip0", 256*MB); - memory_region_add_subregion(addr_space, 0x801a0000000, &s->cchip.region); + memory_region_add_subregion(addr_space, 0x801a0000000ULL, + &s->cchip.region); /* Dchip CSRs, 0x801.B000.0000, 256MB. */ memory_region_init_io(&s->dchip_region, &dchip_ops, s, "dchip0", 256*MB); - memory_region_add_subregion(addr_space, 0x801b0000000, &s->dchip_region); + memory_region_add_subregion(addr_space, 0x801b0000000ULL, + &s->dchip_region); /* Pchip0 PCI memory, 0x800.0000.0000, 4GB. */ memory_region_init(&s->pchip.reg_mem, "pci0-mem", 4*GB); - memory_region_add_subregion(addr_space, 0x80000000000, &s->pchip.reg_mem); + memory_region_add_subregion(addr_space, 0x80000000000ULL, + &s->pchip.reg_mem); /* Pchip0 PCI I/O, 0x801.FC00.0000, 32MB. */ /* ??? Ideally we drop the "system" i/o space on the floor and give the @@ -754,7 +758,8 @@ PCIBus *typhoon_init(ram_addr_t ram_size, qemu_irq *p_rtc_irq, We can't do that until the MEM and IO paths in memory.c are unified. */ memory_region_init_io(&s->pchip.reg_io, &alpha_pci_bw_io_ops, NULL, "pci0-io", 32*MB); - memory_region_add_subregion(addr_space, 0x801fc000000, &s->pchip.reg_io); + memory_region_add_subregion(addr_space, 0x801fc000000ULL, + &s->pchip.reg_io); b = pci_register_bus(&s->host.busdev.qdev, "pci", typhoon_set_irq, sys_map_irq, s, @@ -764,12 +769,14 @@ PCIBus *typhoon_init(ram_addr_t ram_size, qemu_irq *p_rtc_irq, /* Pchip0 PCI special/interrupt acknowledge, 0x801.F800.0000, 64MB. */ memory_region_init_io(&s->pchip.reg_iack, &alpha_pci_iack_ops, b, "pci0-iack", 64*MB); - memory_region_add_subregion(addr_space, 0x801f8000000, &s->pchip.reg_iack); + memory_region_add_subregion(addr_space, 0x801f8000000ULL, + &s->pchip.reg_iack); /* Pchip0 PCI configuration, 0x801.FE00.0000, 16MB. */ memory_region_init_io(&s->pchip.reg_conf, &alpha_pci_conf1_ops, b, "pci0-conf", 16*MB); - memory_region_add_subregion(addr_space, 0x801fe000000, &s->pchip.reg_conf); + memory_region_add_subregion(addr_space, 0x801fe000000ULL, + &s->pchip.reg_conf); /* For the record, these are the mappings for the second PCI bus. We can get away with not implementing them because we indicate |