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authorIgor Mammedov <imammedo@redhat.com>2013-12-13 17:22:06 +0100
committerMichael S. Tsirkin <mst@redhat.com>2013-12-23 13:12:34 +0200
commite4f308bbf9f360ee2af5b94b87aef170d8f20dc4 (patch)
treeb0c6a7c44fe454f24ec7ab6fd8b51203b755b63e /hw/acpi/piix4.c
parent3bcc77ae9935c8c3d10f63492af81f1d7d99d492 (diff)
acpi: piix4: remove not needed GPE0 mask
Hardcoded GPE0 mask isn't really needed. Since GPE0_STS initialized with all bits cleared and only QEMU itself can set bits there (i.e. guest can only clear bits in it). So guest can't triger SCI by setting _STS & _EN bits and there is not reason to mask out not supported _STS bits since they shouldn't be set by QEMU in the first place. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Diffstat (limited to 'hw/acpi/piix4.c')
-rw-r--r--hw/acpi/piix4.c3
1 files changed, 1 insertions, 2 deletions
diff --git a/hw/acpi/piix4.c b/hw/acpi/piix4.c
index 93849c8d36..b4caeab131 100644
--- a/hw/acpi/piix4.c
+++ b/hw/acpi/piix4.c
@@ -122,8 +122,7 @@ static void pm_update_sci(PIIX4PMState *s)
ACPI_BITMASK_POWER_BUTTON_ENABLE |
ACPI_BITMASK_GLOBAL_LOCK_ENABLE |
ACPI_BITMASK_TIMER_ENABLE)) != 0) ||
- (((s->ar.gpe.sts[0] & s->ar.gpe.en[0]) &
- (PIIX4_PCI_HOTPLUG_STATUS | PIIX4_CPU_HOTPLUG_STATUS)) != 0);
+ ((s->ar.gpe.sts[0] & s->ar.gpe.en[0]) != 0);
qemu_set_irq(s->irq, sci_level);
/* schedule a timer interruption if needed */