Compile acpi only once

Use qemu_irqs to trigger CMOS S3 and SMI events.

Avoid using kvm.h, which uses CPUState.

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>

1 files changed, 15 insertions, 10 deletions

diff --git a/hw/acpi.c b/hw/acpi.c
index ad72297a94..33c6bc85cb 100644
--- a/hw/acpi.c
+++ b/hw/acpi.c
@@ -22,7 +22,6 @@
 #include "sysemu.h"
 #include "i2c.h"
 #include "smbus.h"
-#include "kvm.h"
 
 //#define DEBUG
 
@@ -50,6 +49,9 @@ typedef struct PIIX4PMState {
     uint8_t smb_data[32];
     uint8_t smb_index;
     qemu_irq irq;
+    qemu_irq cmos_s3;
+    qemu_irq smi_irq;
+    int kvm_enabled;
 } PIIX4PMState;
 
 #define RSM_STS (1 << 15)
@@ -158,9 +160,9 @@ static void pm_ioport_writew(void *opaque, uint32_t addr, uint32_t val)
                        was caused by power button */
                     s->pmsts |= (RSM_STS | PWRBTN_STS);
                     qemu_system_reset_request();
-#if defined(TARGET_I386)
-                    cmos_set_s3_resume();
-#endif
+                    if (s->cmos_s3) {
+                        qemu_irq_raise(s->cmos_s3);
+                    }
                 default:
                     break;
                 }
@@ -248,7 +250,9 @@ static void pm_smi_writeb(void *opaque, uint32_t addr, uint32_t val)
         }
 
         if (s->dev.config[0x5b] & (1 << 1)) {
-            cpu_interrupt(first_cpu, CPU_INTERRUPT_SMI);
+            if (s->smi_irq) {
+                qemu_irq_raise(s->smi_irq);
+            }
         }
     } else {
         s->apms = val;
@@ -478,7 +482,7 @@ static void piix4_reset(void *opaque)
     pci_conf[0x5a] = 0;
     pci_conf[0x5b] = 0;
 
-    if (kvm_enabled()) {
+    if (s->kvm_enabled) {
         /* Mark SMM as already inited (until KVM supports SMM). */
         pci_conf[0x5B] = 0x02;
     }
@@ -486,7 +490,6 @@ static void piix4_reset(void *opaque)
 
 static void piix4_powerdown(void *opaque, int irq, int power_failing)
 {
-#if defined(TARGET_I386)
     PIIX4PMState *s = opaque;
 
     if (!s) {
@@ -495,11 +498,11 @@ static void piix4_powerdown(void *opaque, int irq, int power_failing)
         s->pmsts |= PWRBTN_EN;
         pm_update_sci(s);
     }
-#endif
 }
 
 i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
-                       qemu_irq sci_irq)
+                       qemu_irq sci_irq, qemu_irq cmos_s3, qemu_irq smi_irq,
+                       int kvm_enabled)
 {
     PIIX4PMState *s;
     uint8_t *pci_conf;
@@ -526,7 +529,7 @@ i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
 
     register_ioport_write(ACPI_DBG_IO_ADDR, 4, 4, acpi_dbg_writel, s);
 
-    if (kvm_enabled()) {
+    if (kvm_enabled) {
         /* Mark SMM as already inited to prevent SMM from running.  KVM does not
          * support SMM mode. */
         pci_conf[0x5B] = 0x02;
@@ -553,6 +556,8 @@ i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
 
     s->smbus = i2c_init_bus(NULL, "i2c");
     s->irq = sci_irq;
+    s->cmos_s3 = cmos_s3;
+    s->smi_irq = smi_irq;
     qemu_register_reset(piix4_reset, s);
 
     return s->smbus;