Handle suspend in qemu (Gleb Natapov)

Reset a PC and tell BIOS that resume from ram is required on the next boot.

Signed-off-by: Gleb Natapov <gleb@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>



git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6080 c046a42c-6fe2-441c-8c8c-71466251a162

1 files changed, 23 insertions, 0 deletions

diff --git a/hw/acpi.c b/hw/acpi.c
index 66a5faa0fd..dd9100aa4b 100644
--- a/hw/acpi.c
+++ b/hw/acpi.c
@@ -53,6 +53,8 @@ typedef struct PIIX4PMState {
     qemu_irq irq;
 } PIIX4PMState;
 
+#define RSM_STS (1 << 15)
+#define PWRBTN_STS (1 << 8)
 #define RTC_EN (1 << 10)
 #define PWRBTN_EN (1 << 8)
 #define GBL_EN (1 << 5)
@@ -151,6 +153,14 @@ static void pm_ioport_writew(void *opaque, uint32_t addr, uint32_t val)
                 case 0: /* soft power off */
                     qemu_system_shutdown_request();
                     break;
+                case 1:
+                    /* RSM_STS should be set on resume. Pretend that resume
+                       was caused by power button */
+                    s->pmsts |= (RSM_STS | PWRBTN_STS);
+                    qemu_system_reset_request();
+#if defined(TARGET_I386)
+                    cmos_set_s3_resume();
+#endif
                 default:
                     break;
                 }
@@ -471,6 +481,17 @@ static int pm_load(QEMUFile* f,void* opaque,int version_id)
     return 0;
 }
 
+static void piix4_reset(void *opaque)
+{
+	PIIX4PMState *s = opaque;
+	uint8_t *pci_conf = s->dev.config;
+
+	pci_conf[0x58] = 0;
+	pci_conf[0x59] = 0;
+	pci_conf[0x5a] = 0;
+	pci_conf[0x5b] = 0;
+}
+
 i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
                        qemu_irq sci_irq)
 {
@@ -527,6 +548,8 @@ i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
 
     s->smbus = i2c_init_bus();
     s->irq = sci_irq;
+    qemu_register_reset(piix4_reset, s);
+
     return s->smbus;
 }