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authorEdgar E. Iglesias <edgar@axis.com>2010-07-24 13:40:05 +0200
committerEdgar E. Iglesias <edgar.iglesias@gmail.com>2010-07-24 13:40:05 +0200
commit36388314febad3d7675ab919287f03733a560ff6 (patch)
tree7becf392376dc244c812b5ccd23fd7c227124a0b /gdbstub.c
parentb2178704e46d061b6162ebd37a19e0db02ccbd77 (diff)
mips: Correct MIPS interrupt glue logic for icount
When hw interrupt pending bits in CP0_Cause are set, the CPU should see the hw interrupt line as active. The CPU may or may not take the interrupt based on internal state (global irq mask etc) but the glue logic shouldn't care. This fixes MIPS external hw interrupts in combination with -icount. Signed-off-by: Edgar E. Iglesias <edgar@axis.com>
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