diff options
| author | Jim Wilson <jimw@sifive.com> | 2019-03-15 03:26:56 -0700 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@sifive.com> | 2019-03-19 05:13:24 -0700 |
| commit | c670970dc069ebaf941a786f0608fca701dcf7d0 (patch) | |
| tree | ee765d1abd7765544d77e6d436a194318835b4d3 /gdb-xml/riscv-64bit-fpu.xml | |
| parent | 1a987a1d5faaff6c3616a857c111aa3fd9d40ffa (diff) | |
RISC-V: Add 64-bit gdb xml files.
Signed-off-by: Jim Wilson <jimw@sifive.com>
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Diffstat (limited to 'gdb-xml/riscv-64bit-fpu.xml')
| -rw-r--r-- | gdb-xml/riscv-64bit-fpu.xml | 56 |
1 files changed, 56 insertions, 0 deletions
diff --git a/gdb-xml/riscv-64bit-fpu.xml b/gdb-xml/riscv-64bit-fpu.xml new file mode 100644 index 0000000000..794854cc01 --- /dev/null +++ b/gdb-xml/riscv-64bit-fpu.xml @@ -0,0 +1,56 @@ +<?xml version="1.0"?> +<!-- Copyright (C) 2018-2019 Free Software Foundation, Inc. + + Copying and distribution of this file, with or without modification, + are permitted in any medium without royalty provided the copyright + notice and this notice are preserved. --> + +<!-- Register numbers are hard-coded in order to maintain backward + compatibility with older versions of tools that didn't use xml + register descriptions. --> + +<!DOCTYPE feature SYSTEM "gdb-target.dtd"> +<feature name="org.gnu.gdb.riscv.fpu"> + + <union id="riscv_double"> + <field name="float" type="ieee_single"/> + <field name="double" type="ieee_double"/> + </union> + + <reg name="ft0" bitsize="64" type="riscv_double" regnum="33"/> + <reg name="ft1" bitsize="64" type="riscv_double"/> + <reg name="ft2" bitsize="64" type="riscv_double"/> + <reg name="ft3" bitsize="64" type="riscv_double"/> + <reg name="ft4" bitsize="64" type="riscv_double"/> + <reg name="ft5" bitsize="64" type="riscv_double"/> + <reg name="ft6" bitsize="64" type="riscv_double"/> + <reg name="ft7" bitsize="64" type="riscv_double"/> + <reg name="fs0" bitsize="64" type="riscv_double"/> + <reg name="fs1" bitsize="64" type="riscv_double"/> + <reg name="fa0" bitsize="64" type="riscv_double"/> + <reg name="fa1" bitsize="64" type="riscv_double"/> + <reg name="fa2" bitsize="64" type="riscv_double"/> + <reg name="fa3" bitsize="64" type="riscv_double"/> + <reg name="fa4" bitsize="64" type="riscv_double"/> + <reg name="fa5" bitsize="64" type="riscv_double"/> + <reg name="fa6" bitsize="64" type="riscv_double"/> + <reg name="fa7" bitsize="64" type="riscv_double"/> + <reg name="fs2" bitsize="64" type="riscv_double"/> + <reg name="fs3" bitsize="64" type="riscv_double"/> + <reg name="fs4" bitsize="64" type="riscv_double"/> + <reg name="fs5" bitsize="64" type="riscv_double"/> + <reg name="fs6" bitsize="64" type="riscv_double"/> + <reg name="fs7" bitsize="64" type="riscv_double"/> + <reg name="fs8" bitsize="64" type="riscv_double"/> + <reg name="fs9" bitsize="64" type="riscv_double"/> + <reg name="fs10" bitsize="64" type="riscv_double"/> + <reg name="fs11" bitsize="64" type="riscv_double"/> + <reg name="ft8" bitsize="64" type="riscv_double"/> + <reg name="ft9" bitsize="64" type="riscv_double"/> + <reg name="ft10" bitsize="64" type="riscv_double"/> + <reg name="ft11" bitsize="64" type="riscv_double"/> + + <reg name="fflags" bitsize="32" type="int" regnum="66"/> + <reg name="frm" bitsize="32" type="int" regnum="67"/> + <reg name="fcsr" bitsize="32" type="int" regnum="68"/> +</feature> |