diff options
| author | Jim Wilson <jimw@sifive.com> | 2019-03-15 03:26:55 -0700 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@sifive.com> | 2019-03-19 05:13:24 -0700 |
| commit | 1a987a1d5faaff6c3616a857c111aa3fd9d40ffa (patch) | |
| tree | dd59f2cd240837224ae74ba592e05a07d5bf8a74 /gdb-xml/riscv-32bit-cpu.xml | |
| parent | 86e2fca2d7f163c50b80254e0afdd4e16378b3bb (diff) | |
RISC-V: Add 32-bit gdb xml files.
Signed-off-by: Jim Wilson <jimw@sifive.com>
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Diffstat (limited to 'gdb-xml/riscv-32bit-cpu.xml')
| -rw-r--r-- | gdb-xml/riscv-32bit-cpu.xml | 47 |
1 files changed, 47 insertions, 0 deletions
diff --git a/gdb-xml/riscv-32bit-cpu.xml b/gdb-xml/riscv-32bit-cpu.xml new file mode 100644 index 0000000000..0d07aaec85 --- /dev/null +++ b/gdb-xml/riscv-32bit-cpu.xml @@ -0,0 +1,47 @@ +<?xml version="1.0"?> +<!-- Copyright (C) 2018-2019 Free Software Foundation, Inc. + + Copying and distribution of this file, with or without modification, + are permitted in any medium without royalty provided the copyright + notice and this notice are preserved. --> + +<!-- Register numbers are hard-coded in order to maintain backward + compatibility with older versions of tools that didn't use xml + register descriptions. --> + +<!DOCTYPE feature SYSTEM "gdb-target.dtd"> +<feature name="org.gnu.gdb.riscv.cpu"> + <reg name="zero" bitsize="32" type="int" regnum="0"/> + <reg name="ra" bitsize="32" type="code_ptr"/> + <reg name="sp" bitsize="32" type="data_ptr"/> + <reg name="gp" bitsize="32" type="data_ptr"/> + <reg name="tp" bitsize="32" type="data_ptr"/> + <reg name="t0" bitsize="32" type="int"/> + <reg name="t1" bitsize="32" type="int"/> + <reg name="t2" bitsize="32" type="int"/> + <reg name="fp" bitsize="32" type="data_ptr"/> + <reg name="s1" bitsize="32" type="int"/> + <reg name="a0" bitsize="32" type="int"/> + <reg name="a1" bitsize="32" type="int"/> + <reg name="a2" bitsize="32" type="int"/> + <reg name="a3" bitsize="32" type="int"/> + <reg name="a4" bitsize="32" type="int"/> + <reg name="a5" bitsize="32" type="int"/> + <reg name="a6" bitsize="32" type="int"/> + <reg name="a7" bitsize="32" type="int"/> + <reg name="s2" bitsize="32" type="int"/> + <reg name="s3" bitsize="32" type="int"/> + <reg name="s4" bitsize="32" type="int"/> + <reg name="s5" bitsize="32" type="int"/> + <reg name="s6" bitsize="32" type="int"/> + <reg name="s7" bitsize="32" type="int"/> + <reg name="s8" bitsize="32" type="int"/> + <reg name="s9" bitsize="32" type="int"/> + <reg name="s10" bitsize="32" type="int"/> + <reg name="s11" bitsize="32" type="int"/> + <reg name="t3" bitsize="32" type="int"/> + <reg name="t4" bitsize="32" type="int"/> + <reg name="t5" bitsize="32" type="int"/> + <reg name="t6" bitsize="32" type="int"/> + <reg name="pc" bitsize="32" type="code_ptr"/> +</feature> |