diff options
| author | Richard Henderson <richard.henderson@linaro.org> | 2023-04-12 13:43:24 +0200 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2023-05-05 10:49:50 +1000 |
| commit | 696bacde957bc5cdabc7710abc316ef56184d928 (patch) | |
| tree | 10b31131c74234c9373c50b35b48fef305a1512f /gdb-xml/riscv-32bit-cpu.xml | |
| parent | 9de7b7b5c7ca8e81c6d62b7c5c5a4753fa597bcb (diff) | |
target/riscv: Set MMU_2STAGE_BIT in riscv_cpu_mmu_index
Incorporate the virt_enabled and MPV checks into the cpu_mmu_index
function, so we don't have to keep doing it within tlb_fill and
subroutines. This also elides a flush on changes to MPV.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-Id: <20230325105429.1142530-17-richard.henderson@linaro.org>
Message-Id: <20230412114333.118895-17-richard.henderson@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'gdb-xml/riscv-32bit-cpu.xml')
0 files changed, 0 insertions, 0 deletions