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authorAndrew Burgess <aburgess@redhat.com>2022-08-31 09:41:23 +0100
committerAlistair Francis <alistair@alistair23.me>2022-09-27 07:04:38 +1000
commit4c0f0b6619126637e802f07c9fe8e9fffbc1c4bb (patch)
treee786058e3f47e69ec54c86019f0bc9919a4bdd4c /gdb-xml/riscv-32bit-cpu.xml
parent94452ac4cf263e8996613db8d981e4ea85bd019a (diff)
target/riscv: remove fixed numbering from GDB xml feature files
The fixed register numbering in the various GDB feature files for RISC-V only exists because these files were originally copied from the GDB source tree. However, the fixed numbering only exists in the GDB source tree so that GDB, when it connects to a target that doesn't provide a target description, will use a specific numbering scheme. That numbering scheme is designed to be compatible with the first versions of QEMU (for RISC-V), that didn't send a target description, and relied on a fixed numbering scheme. Because of the way that QEMU manages its target descriptions, recording the number of registers in each feature, and just relying on GDB's numbering starting from 0, then I propose that we remove all the fixed numbering from the RISC-V feature xml files, and just rely on the standard numbering scheme. Plenty of other targets manage their xml files this way, e.g. ARM, AArch64, Loongarch, m68k, rx, and s390. Signed-off-by: Andrew Burgess <aburgess@redhat.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com> Message-Id: <6069395f90e6fc24dac92197be815fedf42f5974.1661934573.git.aburgess@redhat.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'gdb-xml/riscv-32bit-cpu.xml')
-rw-r--r--gdb-xml/riscv-32bit-cpu.xml6
1 files changed, 1 insertions, 5 deletions
diff --git a/gdb-xml/riscv-32bit-cpu.xml b/gdb-xml/riscv-32bit-cpu.xml
index 0d07aaec85..466f2c0648 100644
--- a/gdb-xml/riscv-32bit-cpu.xml
+++ b/gdb-xml/riscv-32bit-cpu.xml
@@ -5,13 +5,9 @@
are permitted in any medium without royalty provided the copyright
notice and this notice are preserved. -->
-<!-- Register numbers are hard-coded in order to maintain backward
- compatibility with older versions of tools that didn't use xml
- register descriptions. -->
-
<!DOCTYPE feature SYSTEM "gdb-target.dtd">
<feature name="org.gnu.gdb.riscv.cpu">
- <reg name="zero" bitsize="32" type="int" regnum="0"/>
+ <reg name="zero" bitsize="32" type="int"/>
<reg name="ra" bitsize="32" type="code_ptr"/>
<reg name="sp" bitsize="32" type="data_ptr"/>
<reg name="gp" bitsize="32" type="data_ptr"/>