pop ss, mov ss, x and sti disable irqs for the next instruction - began dispatch optimization by adding new x86 cpu 'hidden' flags

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@372 c046a42c-6fe2-441c-8c8c-71466251a162

1 files changed, 0 insertions, 10 deletions

diff --git a/exec.h b/exec.h
index 026daaabe8..b63a66f512 100644
--- a/exec.h
+++ b/exec.h
@@ -61,16 +61,6 @@ extern uint8_t gen_opc_instr_start[OPC_BUF_SIZE];
 
 #if defined(TARGET_I386)
 
-#define GEN_FLAG_CODE32_SHIFT    0
-#define GEN_FLAG_ADDSEG_SHIFT    1
-#define GEN_FLAG_SS32_SHIFT      2
-#define GEN_FLAG_VM_SHIFT        3
-#define GEN_FLAG_ST_SHIFT        4
-#define GEN_FLAG_TF_SHIFT        8 /* same position as eflags */
-#define GEN_FLAG_CPL_SHIFT       9
-#define GEN_FLAG_SOFT_MMU_SHIFT 11
-#define GEN_FLAG_IOPL_SHIFT     12 /* same position as eflags */
-
 void optimize_flags_init(void);
 
 #endif