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authorAnthony Liguori <aliguori@us.ibm.com>2013-07-23 10:57:04 -0500
committerAnthony Liguori <aliguori@us.ibm.com>2013-07-23 10:57:04 -0500
commit3988982c82ad4173dea376fea30e5432d36146db (patch)
treea4f72b53b9db680859ecc16b43dae4f113e1b744 /exec.c
parent931f0adf64261bf7eb3efaafb4430c04a6a3e6f6 (diff)
parent6f152e9bc80aed81ea89aa8ad345cd71326b71fb (diff)
Merge remote-tracking branch 'afaerber/tags/qom-cpu-for-anthony' into staging
QOM CPUState refactorings * Fix NULL pointer dereference in gdbstub * Introduce vaddr type * Introduce CPUClass::set_pc() * Introduce CPUClass::synchronize_from_tb() * Introduce CPUClass::get_phys_page_debug() * Introduce CPUClass::memory_rw_debug() * Move singlestep_enabled and gdb_regs fields out of CPU_COMMON * Adopt CPUState in more APIs * Propagate CPUState in gdbstub # gpg: Signature made Mon 22 Jul 2013 07:50:17 PM CDT using RSA key ID 3E7E013F # gpg: Can't check signature: public key not found # By Andreas Färber (21) and others # Via Andreas Färber * afaerber/tags/qom-cpu-for-anthony: (24 commits) linux-user: Use X86CPU property to retrieve CPUID family gdbstub: Change gdb_register_coprocessor() argument to CPUState cpu: Move gdb_regs field from CPU_COMMON to CPUState gdbstub: Change GDBState::{c,g}_cpu and find_cpu() to CPUState cpu: Introduce CPUClass::memory_rw_debug() for target_memory_rw_debug() exec: Change cpu_memory_rw_debug() argument to CPUState cpu: Turn cpu_get_phys_page_debug() into a CPUClass hook gdbstub: Change gdb_{read,write}_register() argument to CPUState gdbstub: Change gdb_handlesig() argument to CPUState gdbstub: Change syscall callback argument to CPUState kvm: Change kvm_{insert,remove}_breakpoint() argument to CPUState cpu: Change cpu_single_step() argument to CPUState gdbstub: Update gdb_handlesig() and gdb_signalled() Coding Style cpu: Move singlestep_enabled field from CPU_COMMON to CPUState target-alpha: Copy implver to DisasContext target-alpha: Copy singlestep_enabled to DisasContext cpu: Introduce CPUClass::synchronize_from_tb() for cpu_pc_from_tb() target-unicore32: Implement CPUClass::set_pc() target-moxie: Implement CPUClass::set_pc() target-m68k: Implement CPUClass::set_pc() ...
Diffstat (limited to 'exec.c')
-rw-r--r--exec.c36
1 files changed, 20 insertions, 16 deletions
diff --git a/exec.c b/exec.c
index c8658c6f9d..7997002f14 100644
--- a/exec.c
+++ b/exec.c
@@ -415,14 +415,14 @@ void cpu_exec_init(CPUArchState *env)
#if defined(TARGET_HAS_ICE)
#if defined(CONFIG_USER_ONLY)
-static void breakpoint_invalidate(CPUArchState *env, target_ulong pc)
+static void breakpoint_invalidate(CPUState *cpu, target_ulong pc)
{
tb_invalidate_phys_page_range(pc, pc + 1, 0);
}
#else
-static void breakpoint_invalidate(CPUArchState *env, target_ulong pc)
+static void breakpoint_invalidate(CPUState *cpu, target_ulong pc)
{
- tb_invalidate_phys_addr(cpu_get_phys_page_debug(env, pc) |
+ tb_invalidate_phys_addr(cpu_get_phys_page_debug(cpu, pc) |
(pc & ~TARGET_PAGE_MASK));
}
#endif
@@ -525,15 +525,17 @@ int cpu_breakpoint_insert(CPUArchState *env, target_ulong pc, int flags,
bp->flags = flags;
/* keep all GDB-injected breakpoints in front */
- if (flags & BP_GDB)
+ if (flags & BP_GDB) {
QTAILQ_INSERT_HEAD(&env->breakpoints, bp, entry);
- else
+ } else {
QTAILQ_INSERT_TAIL(&env->breakpoints, bp, entry);
+ }
- breakpoint_invalidate(env, pc);
+ breakpoint_invalidate(ENV_GET_CPU(env), pc);
- if (breakpoint)
+ if (breakpoint) {
*breakpoint = bp;
+ }
return 0;
#else
return -ENOSYS;
@@ -564,7 +566,7 @@ void cpu_breakpoint_remove_by_ref(CPUArchState *env, CPUBreakpoint *breakpoint)
#if defined(TARGET_HAS_ICE)
QTAILQ_REMOVE(&env->breakpoints, breakpoint, entry);
- breakpoint_invalidate(env, breakpoint->pc);
+ breakpoint_invalidate(ENV_GET_CPU(env), breakpoint->pc);
g_free(breakpoint);
#endif
@@ -585,14 +587,16 @@ void cpu_breakpoint_remove_all(CPUArchState *env, int mask)
/* enable or disable single step mode. EXCP_DEBUG is returned by the
CPU loop after each instruction */
-void cpu_single_step(CPUArchState *env, int enabled)
+void cpu_single_step(CPUState *cpu, int enabled)
{
#if defined(TARGET_HAS_ICE)
- if (env->singlestep_enabled != enabled) {
- env->singlestep_enabled = enabled;
- if (kvm_enabled())
+ CPUArchState *env = cpu->env_ptr;
+
+ if (cpu->singlestep_enabled != enabled) {
+ cpu->singlestep_enabled = enabled;
+ if (kvm_enabled()) {
kvm_update_guest_debug(env, 0);
- else {
+ } else {
/* must flush all the translated code to avoid inconsistencies */
/* XXX: only flush what is necessary */
tb_flush(env);
@@ -1831,7 +1835,7 @@ MemoryRegion *get_system_io(void)
/* physical memory access (slow version, mainly for debug) */
#if defined(CONFIG_USER_ONLY)
-int cpu_memory_rw_debug(CPUArchState *env, target_ulong addr,
+int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr,
uint8_t *buf, int len, int is_write)
{
int l, flags;
@@ -2602,7 +2606,7 @@ void stq_be_phys(hwaddr addr, uint64_t val)
}
/* virtual memory access for debug (includes writing to ROM) */
-int cpu_memory_rw_debug(CPUArchState *env, target_ulong addr,
+int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr,
uint8_t *buf, int len, int is_write)
{
int l;
@@ -2611,7 +2615,7 @@ int cpu_memory_rw_debug(CPUArchState *env, target_ulong addr,
while (len > 0) {
page = addr & TARGET_PAGE_MASK;
- phys_addr = cpu_get_phys_page_debug(env, page);
+ phys_addr = cpu_get_phys_page_debug(cpu, page);
/* if no physical page mapped, return an error */
if (phys_addr == -1)
return -1;