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| author | Stefan Hajnoczi <stefanha@redhat.com> | 2022-10-05 10:17:02 -0400 |
|---|---|---|
| committer | Stefan Hajnoczi <stefanha@redhat.com> | 2022-10-05 10:17:02 -0400 |
| commit | 4a9c04672a875ed00ea807ea4d552c01f6440bc7 (patch) | |
| tree | 5ae0c7c85d114c608cf6018b8dc50f4feaaa83b8 /event-loop-base.c | |
| parent | fafd35a6dab8e70a7c395aaa8e1273267cf9f3c8 (diff) | |
| parent | ab419fd8a035a65942de4e63effcd55ccbf1a9fe (diff) | |
Merge tag 'pull-tcg-20221004' of https://gitlab.com/rth7680/qemu into staging
Cache CPUClass for use in hot code paths.
Add CPUTLBEntryFull, probe_access_full, tlb_set_page_full.
Add generic support for TARGET_TB_PCREL.
tcg/ppc: Optimize 26-bit jumps using STQ for POWER 2.07
target/sh4: Fix TB_FLAG_UNALIGN
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* tag 'pull-tcg-20221004' of https://gitlab.com/rth7680/qemu:
target/sh4: Fix TB_FLAG_UNALIGN
tcg/ppc: Optimize 26-bit jumps
accel/tcg: Introduce TARGET_TB_PCREL
accel/tcg: Introduce tb_pc and log_pc
hw/core: Add CPUClass.get_pc
include/hw/core: Create struct CPUJumpCache
accel/tcg: Inline tb_flush_jmp_cache
accel/tcg: Do not align tb->page_addr[0]
accel/tcg: Use DisasContextBase in plugin_gen_tb_start
accel/tcg: Use bool for page_find_alloc
accel/tcg: Remove PageDesc code_bitmap
include/exec: Introduce TARGET_PAGE_ENTRY_EXTRA
accel/tcg: Introduce tlb_set_page_full
accel/tcg: Introduce probe_access_full
accel/tcg: Suppress auto-invalidate in probe_access_internal
accel/tcg: Drop addr member from SavedIOTLB
accel/tcg: Rename CPUIOTLBEntry to CPUTLBEntryFull
cputlb: used cached CPUClass in our hot-paths
hw/core/cpu-sysemu: used cached class in cpu_asidx_from_attrs
cpu: cache CPUClass in CPUState for hot code paths
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Diffstat (limited to 'event-loop-base.c')
0 files changed, 0 insertions, 0 deletions