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authorXi Wang <xi.wang@gmail.com>2019-01-26 15:02:56 -0800
committerPalmer Dabbelt <palmer@sifive.com>2019-02-11 15:56:22 -0800
commitff9f31d9a0d45da83f34207b7ccace850cfc465b (patch)
treeb7534aab035d6dc28eac82d16325b8c6f484db19 /dump.c
parent7d04ac38959f8115f2a029d81db1c8aac179aa95 (diff)
target/riscv: fix counter-enable checks in ctr()
Access to a counter in U-mode is permitted only if the corresponding bit is set in both mcounteren and scounteren. The current code ignores mcounteren and checks scounteren only for U-mode access. Signed-off-by: Xi Wang <xi.wang@gmail.com> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
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