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author | Rob Bradford <rbradford@rivosinc.com> | 2023-07-18 14:11:44 +0100 |
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committer | Alistair Francis <alistair.francis@wdc.com> | 2023-07-19 14:37:26 +1000 |
commit | 32be32509987fbe42cf5c2fd3cea3c2ad6eae179 (patch) | |
tree | 9c4908a65064bca27fc47a0ce57df6f88e389d1c /docs | |
parent | a916dc954bb5d5aebe5bfcc222cbe9f984118442 (diff) |
target/riscv: Fix LMUL check to use VLEN
The previous check was failing with:
VLEN=128 ELEN = 64 SEW = 16 and LMUL = 1/8 which is a
valid combination.
Fix the check to allow valid combinations when VLEN is a multiple of
ELEN.
From the specification:
"In general, the requirement is to support LMUL ≥ SEWMIN/ELEN, where
SEWMIN is the narrowest supported SEW value and ELEN is the widest
supported SEW value. In the standard extensions, SEWMIN=8. For standard
vector extensions with ELEN=32, fractional LMULs of 1/2 and 1/4 must be
supported. For standard vector extensions with ELEN=64, fractional LMULs
of 1/2, 1/4, and 1/8 must be supported." Elsewhere in the specification
it makes clear that VLEN>=ELEN.
From inspection this new check allows:
VLEN=ELEN=64 1/2, 1/4, 1/8 for SEW >=8
VLEN=ELEN=32 1/2, 1/4 for SEW >=8
Fixes: d9b7609a1fb2 ("target/riscv: rvv-1.0: configure instructions")
Signed-off-by: Rob Bradford <rbradford@rivosinc.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Message-Id: <20230718131316.12283-2-rbradford@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'docs')
0 files changed, 0 insertions, 0 deletions