Merge tag 'pull-riscv-to-apply-20220525' of github.com:alistair23/qemu into staging

Third RISC-V PR for QEMU 7.1

 * Fixes for accessing VS hypervisor CSRs
 * Improvements for RISC-V Vector extension
 * Fixes for accessing mtimecmp
 * Add new short-isa-string CPU option
 * Improvements to RISC-V machine error handling
 * Disable the "G" extension by default internally, no functional change
 * Enforce floating point extension requirements
 * Cleanup ISA extension checks
 * Resolve redundant property accessors
 * Fix typo of mimpid cpu option
 * Improvements for virtulisation
 * Add zicsr/zifencei to isa_string
 * Support for VxWorks uImage

# -----BEGIN PGP SIGNATURE-----
#
# iQEzBAABCAAdFiEE9sSsRtSTSGjTuM6PIeENKd+XcFQFAmKNX4sACgkQIeENKd+X
# cFRikQgAqdRtGCj9XidnHV7QJkUkckmbqp8ZLwxo3PnoNkKirO8muXlo5jt9veyz
# LGn5nx6rmKX4fjs6CAQ+pNR2Pw2qFfrQiEpQXEhK6Zg6jh576qscqgwhX9JVSmrN
# is7nxpG1J/ZtMzO70DfgzmHO8Ykf+Ca6PNM/4kBftmqsPYjD5nUu/o9RJ98jgpem
# lI3U7sHx9xdoIBUVZO6CwRpmovTAvhz7usRbtKVTSXi7+IElFweyFacxT5X5xvgm
# Wj0GhQaeOYy7sww5XfXClQCeJXJS77ZQiPIaiT0W8vKs5dhY3Eux3zqqt9hWChny
# 0vFoYwHnYS5y8cy56IKeeg0/jnZq+A==
# =NiH/
# -----END PGP SIGNATURE-----
# gpg: Signature made Tue 24 May 2022 03:43:23 PM PDT
# gpg:                using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054
# gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [undefined]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: F6C4 AC46 D493 4868 D3B8  CE8F 21E1 0D29 DF97 7054

* tag 'pull-riscv-to-apply-20220525' of github.com:alistair23/qemu: (23 commits)
  hw/core: loader: Set is_linux to true for VxWorks uImage
  hw/core: Sync uboot_image.h from U-Boot v2022.01
  target/riscv: add zicsr/zifencei to isa_string
  hw/riscv: virt: Fix interrupt parent for dynamic platform devices
  target/riscv: Set [m|s]tval for both illegal and virtual instruction traps
  target/riscv: Fix hstatus.GVA bit setting for traps taken from HS-mode
  target/riscv: Fix csr number based privilege checking
  target/riscv: Fix typo of mimpid cpu option
  target/riscv: check 'I' and 'E' after checking 'G' in riscv_cpu_realize
  hw/riscv/sifive_u: Resolve redundant property accessors
  hw/vfio/pci-quirks: Resolve redundant property getters
  target/riscv: Move/refactor ISA extension checks
  target/riscv: FP extension requirements
  target/riscv: Change "G" expansion
  target/riscv: Disable "G" by default
  target/riscv: Fix coding style on "G" expansion
  hw/riscv: Make CPU config error handling generous (sifive_e/u/opentitan)
  hw/riscv: Make CPU config error handling generous (virt/spike)
  target/riscv: Add short-isa-string option
  target/riscv: Move Zhinx* extensions on ISA string
  ...

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

0 files changed, 0 insertions, 0 deletions