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authorEdgar E. Iglesias <edgar.iglesias@xilinx.com>2021-03-08 23:46:37 +0100
committerPeter Maydell <peter.maydell@linaro.org>2021-03-12 12:40:09 +0000
commita55b441b2ca578417ab3a7a62129cd801e22abf4 (patch)
tree4d9a3015d2e6835ecb5da65f7bdac4675346abb2 /docs/system
parent9f61763574fb19525a68c46f3b8f763e5936a6fe (diff)
hw/arm: versal: Add support for the XRAMs
Connect the support for the Versal Accelerator RAMs (XRAMs). Reviewed-by: Luc Michel <luc@lmichel.fr> Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 20210308224637.2949533-3-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'docs/system')
-rw-r--r--docs/system/arm/xlnx-versal-virt.rst1
1 files changed, 1 insertions, 0 deletions
diff --git a/docs/system/arm/xlnx-versal-virt.rst b/docs/system/arm/xlnx-versal-virt.rst
index 2602d0f995..27f73500d9 100644
--- a/docs/system/arm/xlnx-versal-virt.rst
+++ b/docs/system/arm/xlnx-versal-virt.rst
@@ -30,6 +30,7 @@ Implemented devices:
- 8 ADMA (Xilinx zDMA) channels
- 2 SD Controllers
- OCM (256KB of On Chip Memory)
+- XRAM (4MB of on chip Accelerator RAM)
- DDR memory
QEMU does not yet model any other devices, including the PL and the AI Engine.