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| author | Stefan Weil <sw@weilnetz.de> | 2023-04-09 22:18:28 +0200 |
|---|---|---|
| committer | Thomas Huth <thuth@redhat.com> | 2023-04-20 06:50:10 +0200 |
| commit | 63cec0506e32467ec94db2973a9459147f081abf (patch) | |
| tree | 49743b91b43d02f73e3c20fe6c6c53a2535620af /docs/system | |
| parent | ca45a640b36e2bc7e3129293f3fcae5abc4c26f8 (diff) | |
docs/cxl: Fix sentence
Signed-off-by: Stefan Weil <sw@weilnetz.de>
Message-Id: <20230409201828.1159568-1-sw@weilnetz.de>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Acked-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Diffstat (limited to 'docs/system')
| -rw-r--r-- | docs/system/devices/cxl.rst | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/docs/system/devices/cxl.rst b/docs/system/devices/cxl.rst index f25783a4ec..4c38223069 100644 --- a/docs/system/devices/cxl.rst +++ b/docs/system/devices/cxl.rst @@ -111,7 +111,7 @@ Interfaces provided include: CXL Root Ports (CXL RP) ~~~~~~~~~~~~~~~~~~~~~~~ -A CXL Root Port servers te same purpose as a PCIe Root Port. +A CXL Root Port serves the same purpose as a PCIe Root Port. There are a number of CXL specific Designated Vendor Specific Extended Capabilities (DVSEC) in PCIe Configuration Space and associated component register access via PCI bars. |