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| author | Daniel Henrique Barboza <dbarboza@ventanamicro.com> | 2023-10-20 17:02:47 -0300 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2023-11-07 11:02:17 +1000 |
| commit | 257cfaed47e3263ee3c379ec7a766f5050daa920 (patch) | |
| tree | 47040a2c0ab77f3164b1f34c11af6af429bf8a37 /docs/system/riscv | |
| parent | 4d84cc5887c5ed9a630f5af87e56d64ee0a98c4b (diff) | |
docs/system/riscv: update 'virt' machine core limit
The 'virt' RISC-V machine does not have a 8 core limit. The current
limit is set in include/hw/riscv/virt.h, VIRT_CPUS_MAX, set to 512 at
this moment.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1945
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20231020200247.334403-2-dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'docs/system/riscv')
| -rw-r--r-- | docs/system/riscv/virt.rst | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/docs/system/riscv/virt.rst b/docs/system/riscv/virt.rst index f9a2eac544..f5fa7b8b29 100644 --- a/docs/system/riscv/virt.rst +++ b/docs/system/riscv/virt.rst @@ -12,7 +12,7 @@ Supported devices The ``virt`` machine supports the following devices: -* Up to 8 generic RV32GC/RV64GC cores, with optional extensions +* Up to 512 generic RV32GC/RV64GC cores, with optional extensions * Core Local Interruptor (CLINT) * Platform-Level Interrupt Controller (PLIC) * CFI parallel NOR flash memory |