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| author | Peter Maydell <peter.maydell@linaro.org> | 2021-07-13 15:22:26 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2021-07-18 10:59:47 +0100 |
| commit | c90df7ce4ef50f9cea3c42daea4fc167bb0d9d2e (patch) | |
| tree | 18e58f621aaf4eff99e54181c2c36e02f4f4adb9 /docs/system/arm | |
| parent | 3f65df38e8a5e75ccfd5a641d252ad8882c9e68c (diff) | |
docs: Add skeletal documentation of highbank and midway
Add skeletal documentation for the highbank and midway machines.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20210713142226.19155-4-peter.maydell@linaro.org
Diffstat (limited to 'docs/system/arm')
| -rw-r--r-- | docs/system/arm/highbank.rst | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/docs/system/arm/highbank.rst b/docs/system/arm/highbank.rst new file mode 100644 index 0000000000..bb4965b367 --- /dev/null +++ b/docs/system/arm/highbank.rst @@ -0,0 +1,19 @@ +Calxeda Highbank and Midway (``highbank``, ``midway``) +====================================================== + +``highbank`` is a model of the Calxeda Highbank (ECX-1000) system, +which has four Cortex-A9 cores. + +``midway`` is a model of the Calxeda Midway (ECX-2000) system, +which has four Cortex-A15 cores. + +Emulated devices: + +- L2x0 cache controller +- SP804 dual timer +- PL011 UART +- PL061 GPIOs +- PL031 RTC +- PL022 synchronous serial port controller +- AHCI +- XGMAC ethernet controllers |