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authorDr. David Alan Gilbert <dgilbert@redhat.com>2019-11-04 18:52:02 +0000
committerLaurent Vivier <laurent@vivier.eu>2019-11-06 17:19:40 +0100
commitdf59feb197cda31a8b807c13bf509259db9e018f (patch)
treeb4b7e303da46615f35630214f3be9ac76f040c37 /docs/specs/ppc-xive.rst
parent0fbe394a64ac9ceb13a98f43d078cd48d3006498 (diff)
global: Squash 'the the'
'the' has a tendency to double up; squash them back down. Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20191104185202.102504-1-dgilbert@redhat.com> [lv: removed disas/libvixl/vixl/invalset.h change] Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Diffstat (limited to 'docs/specs/ppc-xive.rst')
-rw-r--r--docs/specs/ppc-xive.rst2
1 files changed, 1 insertions, 1 deletions
diff --git a/docs/specs/ppc-xive.rst b/docs/specs/ppc-xive.rst
index 148d57eb6a..83d43f658b 100644
--- a/docs/specs/ppc-xive.rst
+++ b/docs/specs/ppc-xive.rst
@@ -163,7 +163,7 @@ Interrupt Priority Register (PIPR) is also updated using the IPB. This
register represent the priority of the most favored pending
notification.
-The PIPR is then compared to the the Current Processor Priority
+The PIPR is then compared to the Current Processor Priority
Register (CPPR). If it is more favored (numerically less than), the
CPU interrupt line is raised and the EO bit of the Notification Source
Register (NSR) is updated to notify the presence of an exception for