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| author | Ville Skyttä <ville.skytta@iki.fi> | 2018-06-12 09:51:50 +0300 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2018-07-13 10:16:04 +0100 |
| commit | 9277d81f5c2c6f4d0b5e47c8476eb7ee7e5c0beb (patch) | |
| tree | 40a083214c61e587010e8dbb9465808ec929b548 /docs/devel/multi-thread-tcg.txt | |
| parent | 68f1b569dccdf1bf2935d4175fffe84dae6997fc (diff) | |
docs: Grammar and spelling fixes
Signed-off-by: Ville Skyttä <ville.skytta@iki.fi>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Eric Blake <eblake@redhat.com>
Message-id: 20180612065150.21110-1-ville.skytta@iki.fi
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'docs/devel/multi-thread-tcg.txt')
| -rw-r--r-- | docs/devel/multi-thread-tcg.txt | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/docs/devel/multi-thread-tcg.txt b/docs/devel/multi-thread-tcg.txt index 06530be1e9..782bebc28b 100644 --- a/docs/devel/multi-thread-tcg.txt +++ b/docs/devel/multi-thread-tcg.txt @@ -316,7 +316,7 @@ other cores sharing access to the memory. The classic example is the x86 cmpxchg instruction. The second type offer a pair of load/store instructions which offer a -guarantee that an region of memory has not been touched between the +guarantee that a region of memory has not been touched between the load and store instructions. An example of this is ARM's ldrex/strex pair where the strex instruction will return a flag indicating a successful store only if no other CPU has accessed the memory region |