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| author | Michael Clark <mjc@sifive.com> | 2018-03-09 11:12:31 +1300 |
|---|---|---|
| committer | Michael Clark <mjc@sifive.com> | 2018-03-28 11:12:02 -0700 |
| commit | eab158625703457b8aa6ce6c1b88a0e2c4899cc5 (patch) | |
| tree | 55a0d4fcf82cfe8f98c51af7f865b0a7d79c1e60 /disas | |
| parent | 043289bef4d9c0d277c45695c676a6cc9fca48a0 (diff) | |
RISC-V: Convert cpu definition to future model
- Model borrowed from target/sh4/cpu.c
- Rewrote riscv_cpu_list to use object_class_get_list
- Dropped 'struct RISCVCPUInfo' and used TypeInfo array
- Replaced riscv_cpu_register_types with DEFINE_TYPES
- Marked base class as abstract
- Fixes -cpu list
Cc: Igor Mammedov <imammedo@redhat.com>
Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>
Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Cc: Palmer Dabbelt <palmer@sifive.com>
Signed-off-by: Michael Clark <mjc@sifive.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Diffstat (limited to 'disas')
0 files changed, 0 insertions, 0 deletions