diff options
| author | Leon Alrae <leon.alrae@imgtec.com> | 2014-06-27 08:49:03 +0100 |
|---|---|---|
| committer | Leon Alrae <leon.alrae@imgtec.com> | 2014-10-13 12:38:24 +0100 |
| commit | bf7910c6b1bc47517a9d7a6049d97d056e014eb0 (patch) | |
| tree | e78c66baf97b61ac6540dbb2dd90aa580d5b8777 /disas | |
| parent | fac5a0733013f4e148b406056526f2208464d799 (diff) | |
target-mips: move PREF, CACHE, LLD and SCD instructions
The encoding of PREF, CACHE, LLD and SCD instruction changed in MIPS32R6.
Additionally, the hint codes in PREF instruction greater than or
equal to 24 generate Reserved Instruction Exception.
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Diffstat (limited to 'disas')
| -rw-r--r-- | disas/mips.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/disas/mips.c b/disas/mips.c index f0efa8b29c..cae76ed482 100644 --- a/disas/mips.c +++ b/disas/mips.c @@ -1219,6 +1219,10 @@ const struct mips_opcode mips_builtin_opcodes[] = /* name, args, match, mask, pinfo, membership */ {"ll", "t,o(b)", 0x7c000036, 0xfc00007f, LDD|RD_b|WR_t, 0, I32R6}, {"sc", "t,o(b)", 0x7c000026, 0xfc00007f, LDD|RD_b|WR_t, 0, I32R6}, +{"lld", "t,o(b)", 0x7c000037, 0xfc00007f, LDD|RD_b|WR_t, 0, I64R6}, +{"scd", "t,o(b)", 0x7c000027, 0xfc00007f, LDD|RD_b|WR_t, 0, I64R6}, +{"pref", "h,o(b)", 0x7c000035, 0xfc00007f, RD_b, 0, I32R6}, +{"cache", "k,o(b)", 0x7c000025, 0xfc00007f, RD_b, 0, I32R6}, {"seleqz", "d,v,t", 0x00000035, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I32R6}, {"selnez", "d,v,t", 0x00000037, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I32R6}, {"pref", "k,o(b)", 0xcc000000, 0xfc000000, RD_b, 0, I4|I32|G3 }, |