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| author | Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr> | 2022-01-06 22:00:56 +0100 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2022-01-08 15:46:10 +1000 |
| commit | 2b5470843a6bf10bcc4431d81badec6bfe31f0a7 (patch) | |
| tree | 444313b9acadb43ce1956a288ac5709210e6e9a7 /disas/riscv.c | |
| parent | a1a3aac448cced3161cd0c8a49ac24cd5d58fe14 (diff) | |
target/riscv: array for the 64 upper bits of 128-bit registers
The upper 64-bit of the 128-bit registers have now a place inside
the cpu state structure, and are created as globals for future use.
Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220106210108.138226-7-frederic.petrot@univ-grenoble-alpes.fr
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'disas/riscv.c')
0 files changed, 0 insertions, 0 deletions