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authorMichael Clark <mjc@sifive.com>2018-03-23 01:07:01 -0700
committerMichael Clark <mjc@sifive.com>2018-03-28 11:12:02 -0700
commit33b4f859f1e1ea6722d10c3e9c0e3d85afb44ff4 (patch)
tree463c9021e0e1f31340ac34b700429a7f4daa059c /disas/riscv.c
parenteab158625703457b8aa6ce6c1b88a0e2c4899cc5 (diff)
RISC-V: Fix incorrect disassembly for addiw
This fixes a bug in the disassembler constraints used to lift instructions into pseudo-instructions, whereby addiw instructions are always lifted to sext.w instead of just lifting addiw with a zero immediate. An associated fix has been made to the metadata used to machine generate the disseasembler: https://github.com/michaeljclark/riscv-meta/ commit/4a6b2f3898430768acfe201405224d2ea31e1477 Cc: Sagar Karandikar <sagark@eecs.berkeley.edu> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Cc: Palmer Dabbelt <palmer@sifive.com> Cc: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Michael Clark <mjc@sifive.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'disas/riscv.c')
-rw-r--r--disas/riscv.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/disas/riscv.c b/disas/riscv.c
index 3c17501120..74ad16eacd 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
@@ -600,7 +600,7 @@ static const rvc_constraint rvcc_mv[] = { rvc_imm_eq_zero, rvc_end };
static const rvc_constraint rvcc_not[] = { rvc_imm_eq_n1, rvc_end };
static const rvc_constraint rvcc_neg[] = { rvc_rs1_eq_x0, rvc_end };
static const rvc_constraint rvcc_negw[] = { rvc_rs1_eq_x0, rvc_end };
-static const rvc_constraint rvcc_sext_w[] = { rvc_rs2_eq_x0, rvc_end };
+static const rvc_constraint rvcc_sext_w[] = { rvc_imm_eq_zero, rvc_end };
static const rvc_constraint rvcc_seqz[] = { rvc_imm_eq_p1, rvc_end };
static const rvc_constraint rvcc_snez[] = { rvc_rs1_eq_x0, rvc_end };
static const rvc_constraint rvcc_sltz[] = { rvc_rs2_eq_x0, rvc_end };