diff options
| author | Yongbok Kim <yongbok.kim@mips.com> | 2019-12-20 10:29:34 +0100 |
|---|---|---|
| committer | Aleksandar Markovic <amarkovic@wavecomp.com> | 2020-01-29 19:28:52 +0100 |
| commit | 99029be1c2875cd857614397674bbf563ddb6f91 (patch) | |
| tree | 28c1dde351decde94f717efd13a1db2db8bd561d /disas/mips.c | |
| parent | feafe82cc2289a31b3e3f11dc76f3539ea22d670 (diff) | |
target/mips: Add implementation of GINVT instruction
Implement emulation of GINVT instruction. As QEMU doesn't support
caches and virtualization, this implementation covers only one
instruction (GINVT - Global Invalidate TLB) among all TLB-related
MIPS instructions.
Reviewed-by: Aleksandar Rikalo <aleksandar.rikalo@rt-rk.com>
Signed-off-by: Yongbok Kim <yongbok.kim@mips.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Message-Id: <1579883929-1517-5-git-send-email-aleksandar.markovic@rt-rk.com>
Diffstat (limited to 'disas/mips.c')
| -rw-r--r-- | disas/mips.c | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/disas/mips.c b/disas/mips.c index dfefe5e589..b9a5204304 100644 --- a/disas/mips.c +++ b/disas/mips.c @@ -1409,6 +1409,16 @@ const struct mips_opcode mips_builtin_opcodes[] = {"dvp", "t", 0x41600024, 0xffe0ffff, TRAP|WR_t, 0, I32R6}, {"evp", "", 0x41600004, 0xffffffff, TRAP, 0, I32R6}, {"evp", "t", 0x41600004, 0xffe0ffff, TRAP|WR_t, 0, I32R6}, +{"ginvi", "v", 0x7c00003d, 0xfc1ffcff, TRAP | INSN_TLB, 0, I32R6}, +{"ginvt", "v", 0x7c0000bd, 0xfc1ffcff, TRAP | INSN_TLB, 0, I32R6}, +{"crc32b", "t,v,t", 0x7c00000f, 0xfc00ff3f, WR_d | RD_s | RD_t, 0, I32R6}, +{"crc32h", "t,v,t", 0x7c00004f, 0xfc00ff3f, WR_d | RD_s | RD_t, 0, I32R6}, +{"crc32w", "t,v,t", 0x7c00008f, 0xfc00ff3f, WR_d | RD_s | RD_t, 0, I32R6}, +{"crc32d", "t,v,t", 0x7c0000cf, 0xfc00ff3f, WR_d | RD_s | RD_t, 0, I64R6}, +{"crc32cb", "t,v,t", 0x7c00010f, 0xfc00ff3f, WR_d | RD_s | RD_t, 0, I32R6}, +{"crc32ch", "t,v,t", 0x7c00014f, 0xfc00ff3f, WR_d | RD_s | RD_t, 0, I32R6}, +{"crc32cw", "t,v,t", 0x7c00018f, 0xfc00ff3f, WR_d | RD_s | RD_t, 0, I32R6}, +{"crc32cd", "t,v,t", 0x7c0001cf, 0xfc00ff3f, WR_d | RD_s | RD_t, 0, I64R6}, /* MSA */ {"sll.b", "+d,+e,+f", 0x7800000d, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, |