diff options
| author | Leon Alrae <leon.alrae@imgtec.com> | 2014-07-07 11:24:00 +0100 |
|---|---|---|
| committer | Leon Alrae <leon.alrae@imgtec.com> | 2014-11-03 11:48:34 +0000 |
| commit | 9456c2fbcd82dd82328ac6e7602a815582b1043e (patch) | |
| tree | 7a2f9f2763b0945ec990ae22f3847476f89c5de5 /disas/mips.c | |
| parent | 92ceb440d47b9ef3ba860cdc75a7e31563a7dc0c (diff) | |
target-mips: add TLBINV support
For Standard TLB configuration (Config.MT=1):
TLBINV invalidates a set of TLB entries based on ASID. The virtual address is
ignored in the entry match. TLB entries which have their G bit set to 1 are not
modified.
TLBINVF causes all entries to be invalidated.
Single TLB entry can be marked as invalid on TLB entry write by having
EntryHi.EHINV set to 1.
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
Reviewed-by: Yongbok Kim <yongbok.kim@imgtec.com>
Diffstat (limited to 'disas/mips.c')
| -rw-r--r-- | disas/mips.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/disas/mips.c b/disas/mips.c index 7297825138..4974bc0da2 100644 --- a/disas/mips.c +++ b/disas/mips.c @@ -2410,6 +2410,8 @@ const struct mips_opcode mips_builtin_opcodes[] = {"tlbp", "", 0x42000008, 0xffffffff, INSN_TLB, 0, I1 }, {"tlbr", "", 0x42000001, 0xffffffff, INSN_TLB, 0, I1 }, {"tlbwi", "", 0x42000002, 0xffffffff, INSN_TLB, 0, I1 }, +{"tlbinv", "", 0x42000003, 0xffffffff, INSN_TLB, 0, I32 }, +{"tlbinvf", "", 0x42000004, 0xffffffff, INSN_TLB, 0, I32 }, {"tlbwr", "", 0x42000006, 0xffffffff, INSN_TLB, 0, I1 }, {"tlti", "s,j", 0x040a0000, 0xfc1f0000, RD_s|TRAP, 0, I2 }, {"tlt", "s,t", 0x00000032, 0xfc00ffff, RD_s|RD_t|TRAP, 0, I2 }, |