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| author | Peter Maydell <peter.maydell@linaro.org> | 2019-01-03 13:26:30 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2019-01-03 13:26:30 +0000 |
| commit | 20d6c7312f1b812bb9c750f4087f69ac8485cc90 (patch) | |
| tree | 706c942dd9982802f647e20be3864b6a2a8e44d1 /default-configs | |
| parent | 1b3e80082bcd9b760113bbc023496cd22efad2dc (diff) | |
| parent | 7b91ae7d7944056c5e8045342e4039e978e43c82 (diff) | |
Merge remote-tracking branch 'remotes/palmer/tags/riscv-for-master-3.2-part1' into staging
RISC-V Changes for 3.2, Part 1
This pull request contains the first set of RISC-V patches I'd like to
target for the 3.2 development cycle. It's really just a collection of
bug fixes with one major new feature: PCIe can now be attached to RISC-V
guests.
This has passed my usual test of booting the latest Linux RC into a
Fedora disk image on the virt machine.
# gpg: Signature made Fri 21 Dec 2018 16:01:29 GMT
# gpg: using RSA key EF4CA1502CCBAB41
# gpg: Good signature from "Palmer Dabbelt <palmer@dabbelt.com>"
# gpg: aka "Palmer Dabbelt <palmer@sifive.com>"
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 00CE 76D1 8349 60DF CE88 6DF8 EF4C A150 2CCB AB41
* remotes/palmer/tags/riscv-for-master-3.2-part1:
MAINTAINERS: Mark RISC-V as Supported
riscv/cpu: use device_class_set_parent_realize
target/riscv/pmp.c: Fix pmp_decode_napot()
sifive_uart: Implement interrupt pending register
RISC-V: Enable second UART on sifive_e and sifive_u
RISC-V: Fix PLIC pending bitfield reads
RISC-V: Fix CLINT timecmp low 32-bit writes
RISC-V: Add hartid and \n to interrupt logging
sifive_u: Set 'clock-frequency' DT property for SiFive UART
sifive_u: Add clock DT node for GEM ethernet
riscv: Enable VGA and PCIE_VGA
hw/riscv/virt: Connect the gpex PCIe
hw/riscv/virt: Adjust memory layout spacing
hw/riscv/virt: Increase the number of interrupts
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'default-configs')
| -rw-r--r-- | default-configs/riscv32-softmmu.mak | 8 | ||||
| -rw-r--r-- | default-configs/riscv64-softmmu.mak | 8 |
2 files changed, 14 insertions, 2 deletions
diff --git a/default-configs/riscv32-softmmu.mak b/default-configs/riscv32-softmmu.mak index 7937c69e22..dbc9398284 100644 --- a/default-configs/riscv32-softmmu.mak +++ b/default-configs/riscv32-softmmu.mak @@ -1,7 +1,13 @@ # Default configuration for riscv-softmmu +include pci.mak + CONFIG_SERIAL=y CONFIG_VIRTIO_MMIO=y -include virtio.mak CONFIG_CADENCE=y + +CONFIG_PCI_GENERIC=y + +CONFIG_VGA=y +CONFIG_VGA_PCI=y diff --git a/default-configs/riscv64-softmmu.mak b/default-configs/riscv64-softmmu.mak index 7937c69e22..dbc9398284 100644 --- a/default-configs/riscv64-softmmu.mak +++ b/default-configs/riscv64-softmmu.mak @@ -1,7 +1,13 @@ # Default configuration for riscv-softmmu +include pci.mak + CONFIG_SERIAL=y CONFIG_VIRTIO_MMIO=y -include virtio.mak CONFIG_CADENCE=y + +CONFIG_PCI_GENERIC=y + +CONFIG_VGA=y +CONFIG_VGA_PCI=y |