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| author | Richard Henderson <richard.henderson@linaro.org> | 2019-09-30 04:36:26 +0000 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2019-10-14 07:10:44 -0700 |
| commit | 6e11cde15074a9b218d89bfb9bbf8ac6f7a881c5 (patch) | |
| tree | dc9af042fc160812db6780a055caa15f54966542 /cpus.c | |
| parent | d7cd6a2f251c54c989fa35858beafe4a25c789af (diff) | |
tcg/ppc: Update vector support for v3.00 load/store
These new instructions are a mix of those like LXSD that are
only conditional only on MSR.VEC and those like LXV that are
conditional on MSR.VEC for TX=1. Thus, in the end, we can
consider all of these as Altivec instructions.
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'cpus.c')
0 files changed, 0 insertions, 0 deletions