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authorIvan Klokov <ivan.klokov@syntacore.com>2023-02-27 12:02:28 +0300
committerAlistair Francis <alistair.francis@wdc.com>2023-03-14 16:36:30 +1000
commit13e269f64aae28b76a9909eed445dfe526086766 (patch)
tree38daa5568e40dbff5c97e34998732b5703a4fe0b /cpu.c
parent284c52eec2d0a1b9c47f06c3eee46762c5fc0915 (diff)
disas/riscv: Fix slli_uw decoding
The decoding of the slli_uw currently contains decoding error: shamt part of opcode has six bits, not five. Fixes 3de1fb71("target/riscv: update disas.c for xnor/orn/andn and slli.uw") Signed-off-by: Ivan Klokov <ivan.klokov@syntacore.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@vrull.eu> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230227090228.17117-1-ivan.klokov@syntacore.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'cpu.c')
0 files changed, 0 insertions, 0 deletions