diff options
| author | bellard <bellard@c046a42c-6fe2-441c-8c8c-71466251a162> | 2003-07-07 11:30:47 +0000 |
|---|---|---|
| committer | bellard <bellard@c046a42c-6fe2-441c-8c8c-71466251a162> | 2003-07-07 11:30:47 +0000 |
| commit | 3c1cf9fa865927759a78d476a218a7759fb38fb4 (patch) | |
| tree | 3685bb1a07b7db30483ecd3282adbb321866324a /cpu-i386.h | |
| parent | 1f47a9223ebe3d0c9c779f72341afc10c206d574 (diff) | |
dummy rdmsr and wrmsr support - xor reg, reg optimization
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@311 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'cpu-i386.h')
| -rw-r--r-- | cpu-i386.h | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/cpu-i386.h b/cpu-i386.h index 4029746c80..e6318fb7f2 100644 --- a/cpu-i386.h +++ b/cpu-i386.h @@ -125,6 +125,15 @@ #define PG_ERROR_U_MASK 0x04 #define PG_ERROR_RSVD_MASK 0x08 +#define MSR_IA32_APICBASE 0x1b +#define MSR_IA32_APICBASE_BSP (1<<8) +#define MSR_IA32_APICBASE_ENABLE (1<<11) +#define MSR_IA32_APICBASE_BASE (0xfffff<<12) + +#define MSR_IA32_SYSENTER_CS 0x174 +#define MSR_IA32_SYSENTER_ESP 0x175 +#define MSR_IA32_SYSENTER_EIP 0x176 + #define EXCP00_DIVZ 0 #define EXCP01_SSTP 1 #define EXCP02_NMI 2 @@ -244,6 +253,11 @@ typedef struct CPUX86State { SegmentCache tr; SegmentCache gdt; /* only base and limit are used */ SegmentCache idt; /* only base and limit are used */ + + /* sysenter registers */ + uint32_t sysenter_cs; + uint32_t sysenter_esp; + uint32_t sysenter_eip; /* exception/interrupt handling */ jmp_buf jmp_env; |