diff options
| author | bellard <bellard@c046a42c-6fe2-441c-8c8c-71466251a162> | 2005-11-20 10:32:34 +0000 |
|---|---|---|
| committer | bellard <bellard@c046a42c-6fe2-441c-8c8c-71466251a162> | 2005-11-20 10:32:34 +0000 |
| commit | a316d3353cefb6634f8007c8bb18f4744a66766b (patch) | |
| tree | 4f3161b2dc1f0697e94ae890f3a40fb792c5ae11 /cpu-defs.h | |
| parent | 6e256c935cbd5ce9bf1891477188549bbb43e55b (diff) | |
added CPU_COMMON and CPUState.tb_jmp_cache[]
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1630 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'cpu-defs.h')
| -rw-r--r-- | cpu-defs.h | 29 |
1 files changed, 29 insertions, 0 deletions
diff --git a/cpu-defs.h b/cpu-defs.h index 912133ee6c..fb4f8e8a29 100644 --- a/cpu-defs.h +++ b/cpu-defs.h @@ -77,6 +77,9 @@ typedef unsigned long ram_addr_t; #define MAX_BREAKPOINTS 32 +#define TB_JMP_CACHE_BITS 12 +#define TB_JMP_CACHE_SIZE (1 << TB_JMP_CACHE_BITS) + #define CPU_TLB_SIZE 256 typedef struct CPUTLBEntry { @@ -91,4 +94,30 @@ typedef struct CPUTLBEntry { target_phys_addr_t addend; } CPUTLBEntry; +#define CPU_COMMON \ + struct TranslationBlock *current_tb; /* currently executing TB */ \ + /* soft mmu support */ \ + /* in order to avoid passing too many arguments to the memory \ + write helpers, we store some rarely used information in the CPU \ + context) */ \ + unsigned long mem_write_pc; /* host pc at which the memory was \ + written */ \ + target_ulong mem_write_vaddr; /* target virtual addr at which the \ + memory was written */ \ + /* 0 = kernel, 1 = user */ \ + CPUTLBEntry tlb_read[2][CPU_TLB_SIZE]; \ + CPUTLBEntry tlb_write[2][CPU_TLB_SIZE]; \ + struct TranslationBlock *tb_jmp_cache[TB_JMP_CACHE_SIZE]; \ + \ + /* from this point: preserved by CPU reset */ \ + /* ice debug support */ \ + target_ulong breakpoints[MAX_BREAKPOINTS]; \ + int nb_breakpoints; \ + int singlestep_enabled; \ + \ + /* user data */ \ + void *opaque; + + + #endif |