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| author | ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162> | 2007-10-28 19:45:05 +0000 |
|---|---|---|
| committer | ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162> | 2007-10-28 19:45:05 +0000 |
| commit | 623a930ec30a75e6d6482ca8208d7bf1ca8d359b (patch) | |
| tree | 6953605abd679c357ffba546fd43907a4ce9ea0e /cpu-defs.h | |
| parent | 8e129e0748f866d730f1e39bff296219fedac244 (diff) | |
Implement missing MIPS supervisor mode bits.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3472 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'cpu-defs.h')
| -rw-r--r-- | cpu-defs.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/cpu-defs.h b/cpu-defs.h index 86557e442b..8414aca221 100644 --- a/cpu-defs.h +++ b/cpu-defs.h @@ -122,7 +122,7 @@ typedef struct CPUTLBEntry { written */ \ target_ulong mem_write_vaddr; /* target virtual addr at which the \ memory was written */ \ - /* 0 = kernel, 1 = user */ \ + /* The meaning of the MMU modes is defined in the target code. */ \ CPUTLBEntry tlb_table[NB_MMU_MODES][CPU_TLB_SIZE]; \ struct TranslationBlock *tb_jmp_cache[TB_JMP_CACHE_SIZE]; \ \ |