diff options
| author | Jan Kiszka <jan.kiszka@siemens.com> | 2012-02-17 18:31:17 +0100 |
|---|---|---|
| committer | Avi Kivity <avi@redhat.com> | 2012-02-18 12:15:55 +0200 |
| commit | d362e757d35727c915052974086f8687d3557431 (patch) | |
| tree | 4b40ca889cd09a8f0f42b86410a808c6d3a9da1b /cpu-all.h | |
| parent | d798e97456658ea7605303b7c69b04ec7df95c10 (diff) | |
target-i386: Add infrastructure for reporting TPR MMIO accesses
This will allow the APIC core to file a TPR access report. Depending on
the accelerator and kernel irqchip mode, it will either be delivered
right away or queued for later reporting.
In TCG mode, we can restart the triggering instruction and can therefore
forward the event directly. KVM does not allows us to restart, so we
postpone the delivery of events recording in the user space APIC until
the current instruction is completed.
Note that KVM without in-kernel irqchip will report the address after
the instruction that triggered the access.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Avi Kivity <avi@redhat.com>
Diffstat (limited to 'cpu-all.h')
| -rw-r--r-- | cpu-all.h | 3 |
1 files changed, 2 insertions, 1 deletions
@@ -375,8 +375,9 @@ DECLARE_TLS(CPUState *,cpu_single_env); #define CPU_INTERRUPT_TGT_INT_0 0x0100 #define CPU_INTERRUPT_TGT_INT_1 0x0400 #define CPU_INTERRUPT_TGT_INT_2 0x0800 +#define CPU_INTERRUPT_TGT_INT_3 0x2000 -/* First unused bit: 0x2000. */ +/* First unused bit: 0x4000. */ /* The set of all bits that should be masked when single-stepping. */ #define CPU_INTERRUPT_SSTEP_MASK \ |