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| author | Richard Henderson <richard.henderson@linaro.org> | 2020-05-13 09:32:31 -0700 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2020-05-14 15:03:08 +0100 |
| commit | 6ccd48d4ea244c1c46a24dfa50bfb547f11422dd (patch) | |
| tree | 85b28fdda20fdc18b125f119b48255161df4b7a8 /contrib/ivshmem-server | |
| parent | 631e565450c483e0622eec3d8b61d7fa41d16bca (diff) | |
target/arm: Create gen_gvec_{u,s}{rshr,rsra}
Create vectorized versions of handle_shri_with_rndacc
for shift+round and shift+round+accumulate. Add out-of-line
helpers in preparation for longer vector lengths from SVE.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200513163245.17915-3-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'contrib/ivshmem-server')
0 files changed, 0 insertions, 0 deletions