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author | Peter Maydell <peter.maydell@linaro.org> | 2018-02-08 17:41:15 +0000 |
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committer | Peter Maydell <peter.maydell@linaro.org> | 2018-02-08 17:41:15 +0000 |
commit | 04bb7fe2bf55bdf66d5b7a5a719b40bbb4048178 (patch) | |
tree | d6352968c57e2255ef66f0ba4a696ba82cc9f3ca /configure | |
parent | 008a51bbb343972dd8cf09126da8c3b87f4e1c96 (diff) | |
parent | 14e4c1e2355473ccb2939afc69ac8f25de103b92 (diff) |
Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20180208' into staging
tcg generic vectors
# gpg: Signature made Thu 08 Feb 2018 16:47:16 GMT
# gpg: using RSA key 64DF38E8AF7E215F
# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>"
# Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F
* remotes/rth/tags/pull-tcg-20180208:
tcg/aarch64: Add vector operations
tcg/i386: Add vector operations
target/arm: Use vector infrastructure for aa64 orr/bic immediate
target/arm: Use vector infrastructure for aa64 multiplies
target/arm: Use vector infrastructure for aa64 compares
target/arm: Use vector infrastructure for aa64 constant shifts
target/arm: Use vector infrastructure for aa64 dup/movi
target/arm: Use vector infrastructure for aa64 mov/not/neg
target/arm: Use vector infrastructure for aa64 add/sub/logic
target/arm: Align vector registers
tcg/optimize: Handle vector opcodes during optimize
tcg: Add generic vector helpers with a scalar operand
tcg: Add generic helpers for saturating arithmetic
tcg: Add generic vector ops for multiplication
tcg: Add generic vector ops for comparisons
tcg: Add generic vector ops for constant shifts
tcg: Add generic vector expanders
tcg: Standardize integral arguments to expanders
tcg: Add types and basic operations for host vectors
tcg: Allow multiple word entries into the constant pool
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'configure')
-rwxr-xr-x | configure | 48 |
1 files changed, 48 insertions, 0 deletions
@@ -5001,6 +5001,50 @@ if compile_prog "" "" ; then fi ######################################## +# See if 16-byte vector operations are supported. +# Even without a vector unit the compiler may expand these. +# There is a bug in old GCC for PPC that crashes here. +# Unfortunately it's the system compiler for Centos 7. + +cat > $TMPC << EOF +typedef unsigned char U1 __attribute__((vector_size(16))); +typedef unsigned short U2 __attribute__((vector_size(16))); +typedef unsigned int U4 __attribute__((vector_size(16))); +typedef unsigned long long U8 __attribute__((vector_size(16))); +typedef signed char S1 __attribute__((vector_size(16))); +typedef signed short S2 __attribute__((vector_size(16))); +typedef signed int S4 __attribute__((vector_size(16))); +typedef signed long long S8 __attribute__((vector_size(16))); +static U1 a1, b1; +static U2 a2, b2; +static U4 a4, b4; +static U8 a8, b8; +static S1 c1; +static S2 c2; +static S4 c4; +static S8 c8; +static int i; +int main(void) +{ + a1 += b1; a2 += b2; a4 += b4; a8 += b8; + a1 -= b1; a2 -= b2; a4 -= b4; a8 -= b8; + a1 *= b1; a2 *= b2; a4 *= b4; a8 *= b8; + a1 &= b1; a2 &= b2; a4 &= b4; a8 &= b8; + a1 |= b1; a2 |= b2; a4 |= b4; a8 |= b8; + a1 ^= b1; a2 ^= b2; a4 ^= b4; a8 ^= b8; + a1 <<= i; a2 <<= i; a4 <<= i; a8 <<= i; + a1 >>= i; a2 >>= i; a4 >>= i; a8 >>= i; + c1 >>= i; c2 >>= i; c4 >>= i; c8 >>= i; + return 0; +} +EOF + +vector16=no +if compile_prog "" "" ; then + vector16=yes +fi + +######################################## # check if getauxval is available. getauxval=no @@ -6329,6 +6373,10 @@ if test "$atomic64" = "yes" ; then echo "CONFIG_ATOMIC64=y" >> $config_host_mak fi +if test "$vector16" = "yes" ; then + echo "CONFIG_VECTOR16=y" >> $config_host_mak +fi + if test "$getauxval" = "yes" ; then echo "CONFIG_GETAUXVAL=y" >> $config_host_mak fi |