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authorSai Pavan Boddu <sai.pavan.boddu@xilinx.com>2015-05-29 11:52:35 +0530
committerMichael Tokarev <mjt@tls.msk.ru>2015-06-03 16:03:03 +0300
commit2801339f2fb2534ccf01561d274398328bdd446d (patch)
tree96962ba0a29c40330dd3687e4913524d835bb71e /configure
parent8b8f1c7e9ddb2e88a144638f6527bf70e32343e3 (diff)
cadence_gem: Fix Rx buffer size field mask
This patch corrects the Rx buffer size field mask to mask bits 23 to 16 to match Xilinx UG585 documentation. Signed-off-by: Sai Pavan Boddu <saipava@xilinx.com> Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
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