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author | Peter Maydell <peter.maydell@linaro.org> | 2015-09-15 17:24:27 +0100 |
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committer | Peter Maydell <peter.maydell@linaro.org> | 2015-09-15 17:24:28 +0100 |
commit | 1a3abef74b5df6d6d3e851aaeacac8f265adcf80 (patch) | |
tree | 64deb73d56895ccebd70c2d8db0527e4b362f76c /configure | |
parent | 619622424dba749feef752d76d79ef2569f7f250 (diff) | |
parent | 461aa6783eec27f209b026c6647fc7a83b2997cd (diff) |
Merge remote-tracking branch 'remotes/rth/tags/pull-tile-20150915' into staging
TileGX basic instructions
# gpg: Signature made Tue 15 Sep 2015 15:57:08 BST using RSA key ID 4DD0279B
# gpg: Good signature from "Richard Henderson <rth7680@gmail.com>"
# gpg: aka "Richard Henderson <rth@redhat.com>"
# gpg: aka "Richard Henderson <rth@twiddle.net>"
* remotes/rth/tags/pull-tile-20150915: (35 commits)
target-tilegx: Handle v1shl, v1shru, v1shrs
target-tilegx: Handle v1shli, v1shrui
target-tilegx: Handle v4int_l/h
target-tilegx: Handle atomic instructions
target-tilegx: Handle mtspr, mfspr
target-tilegx: Handle v1cmpeq, v1cmpne
target-tilegx: Handle mask instructions
target-tilegx: Handle scalar multiply instructions
target-tilegx: Handle conditional move instructions
target-tilegx: Handle shift instructions
target-tilegx: Handle bitfield instructions
target-tilegx: Implement system and memory management instructions
target-tilegx: Handle comparison instructions
target-tilegx: Handle conditional branch instructions
target-tilegx: Handle unconditional jump instructions
target-tilegx: Handle post-increment load and store instructions
target-tilegx: Handle basic load and store instructions
target-tilegx: Handle most bit manipulation instructions
target-arm: Use new revbit functions
host-utils: Add revbit functions
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'configure')
-rwxr-xr-x | configure | 2 |
1 files changed, 2 insertions, 0 deletions
@@ -5441,6 +5441,8 @@ case "$target_name" in s390x) gdb_xml_files="s390x-core64.xml s390-acr.xml s390-fpr.xml s390-vx.xml s390-cr.xml" ;; + tilegx) + ;; tricore) ;; unicore32) |