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authorGeorg Kotheimer <georg.kotheimer@kernkonzept.com>2021-03-19 15:14:59 +0100
committerAlistair Francis <alistair.francis@wdc.com>2021-03-22 21:54:40 -0400
commitec352d0cab58a7bf66019057d0dfcffd9e7785a8 (patch)
tree9a044109c6972d89378f4857a286ca4a478621fb /chardev/char-socket.c
parent9d5451e077cd84809bcdf460c39b5f4fec17fc79 (diff)
target/riscv: Add proper two-stage lookup exception detection
The current two-stage lookup detection in riscv_cpu_do_interrupt falls short of its purpose, as all it checks is whether two-stage address translation either via the hypervisor-load store instructions or the MPRV feature would be allowed. What we really need instead is whether two-stage address translation was active when the exception was raised. However, in riscv_cpu_do_interrupt we do not have the information to reliably detect this. Therefore, when we raise a memory fault exception we have to record whether two-stage address translation is active. Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210319141459.1196741-1-georg.kotheimer@kernkonzept.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'chardev/char-socket.c')
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