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authorRichard Henderson <richard.henderson@linaro.org>2021-10-18 09:16:51 -0700
committerRichard Henderson <richard.henderson@linaro.org>2021-10-18 09:16:51 -0700
commit9c050b661d3a43dfe2fd44106e559b39706d1296 (patch)
tree78b1882ffceb38dee407d12db25d161c2b45db2a /bsd-user/signal.c
parentc148a0572130ff485cd2249fbdd1a3260d5e10a4 (diff)
parent2792cf20ca7eed0e354a0ed731422411faca4908 (diff)
Merge remote-tracking branch 'remotes/philmd/tags/mips-20211018' into staging
MIPS patches queue Hardware emulation: - Generate FDT blob for Boston machine (Jiaxun) - VIA chipset cleanups (Zoltan) TCG: - Use tcg_constant() in Compact branch and MSA opcodes - Restrict nanoMIPS DSP MULT[U] opcode accumulator to Rel6 - Fix DEXTRV_S.H DSP opcode - Remove unused TCG temporary for some DSP opcodes # gpg: Signature made Sun 17 Oct 2021 03:50:57 PM PDT # gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE # gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full] * remotes/philmd/tags/mips-20211018: via-ide: Avoid using isa_get_irq() vt82c686: Add a method to VIA_ISA to raise ISA interrupts vt82c686: Move common code to via_isa_realize via-ide: Set user_creatable to false target/mips: Remove unused TCG temporary in gen_mipsdsp_accinsn() target/mips: Fix DEXTRV_S.H DSP opcode target/mips: Use tcg_constant_tl() in gen_compute_compact_branch() target/mips: Use explicit extract32() calls in gen_msa_i5() target/mips: Use tcg_constant_i32() in gen_msa_3rf() target/mips: Use tcg_constant_i32() in gen_msa_2r() target/mips: Use tcg_constant_i32() in gen_msa_2rf() target/mips: Use tcg_constant_i32() in gen_msa_elm_df() target/mips: Remove unused register from MSA 2R/2RF instruction format hw/mips/boston: Add FDT generator hw/mips/boston: Allow loading elf kernel and dtb hw/mips/boston: Massage memory map information target/mips: Check nanoMIPS DSP MULT[U] accumulator with Release 6 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'bsd-user/signal.c')
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