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authorLi Zhijian <lizhijian@fujitsu.com>2024-01-26 12:01:27 +0000
committerMichael Tokarev <mjt@tls.msk.ru>2024-02-14 21:42:04 +0300
commitbbe51d6ea3a9adcca3b46ce8f19b9b4ead488e28 (patch)
treed300944a74757b1e64284741401c3d1d21ecbf00 /audio
parentbdd3159ad724e4e0aad571b4352b288b8f947ddd (diff)
hw/cxl: Pass CXLComponentState to cache_mem_ops
cache_mem_ops.{read,write}() interprets opaque as CXLComponentState(cxl_cstate) instead of ComponentRegisters(cregs). Fortunately, cregs is the first member of cxl_cstate, so their values are the same. Fixes: 9e58f52d3f8 ("hw/cxl/component: Introduce CXL components (8.1.x, 8.2.5)") Reviewed-by: Fan Ni <fan.ni@samsung.com> Signed-off-by: Li Zhijian <lizhijian@fujitsu.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Message-Id: <20240126120132.24248-8-Jonathan.Cameron@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> (cherry picked from commit 729d45a6af06753d3e330f589c248fe9687c5cd5) Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
Diffstat (limited to 'audio')
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