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authorMichael Clark <mjc@sifive.com>2018-03-03 01:32:59 +1300
committerMichael Clark <mjc@sifive.com>2018-03-07 08:30:28 +1300
commit25fa194b7b11901561532e435beb83d046899f7a (patch)
tree361c143f38183b884bcac16e30d69791c3c40492 /arch_init.c
parenta7240d1e4aac4cd4542d68f3cc722939550da6af (diff)
RISC-V Build Infrastructure
This adds RISC-V into the build system enabling the following targets: - riscv32-softmmu - riscv64-softmmu - riscv32-linux-user - riscv64-linux-user This adds defaults configs for RISC-V, enables the build for the RISC-V CPU core, hardware, and Linux User Emulation. The 'qemu-binfmt-conf.sh' script is updated to add the RISC-V ELF magic. Expected checkpatch errors for consistency reasons: ERROR: line over 90 characters FILE: scripts/qemu-binfmt-conf.sh Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Sagar Karandikar <sagark@eecs.berkeley.edu> Signed-off-by: Michael Clark <mjc@sifive.com>
Diffstat (limited to 'arch_init.c')
-rw-r--r--arch_init.c2
1 files changed, 2 insertions, 0 deletions
diff --git a/arch_init.c b/arch_init.c
index 46d03f550d..6ee07478bd 100644
--- a/arch_init.c
+++ b/arch_init.c
@@ -71,6 +71,8 @@ int graphic_depth = 32;
#define QEMU_ARCH QEMU_ARCH_OPENRISC
#elif defined(TARGET_PPC)
#define QEMU_ARCH QEMU_ARCH_PPC
+#elif defined(TARGET_RISCV)
+#define QEMU_ARCH QEMU_ARCH_RISCV
#elif defined(TARGET_S390X)
#define QEMU_ARCH QEMU_ARCH_S390X
#elif defined(TARGET_SH4)