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authorPeter Maydell <peter.maydell@linaro.org>2021-05-20 14:09:05 +0100
committerPeter Maydell <peter.maydell@linaro.org>2021-05-25 16:01:43 +0100
commit659f042ba8ef80ca1053042a781a4488f9a587dc (patch)
tree0eb3cb91d68df9b450f39799770991aa548ab7ed /accel
parentcbb563887781d813e67c59b68dd76891cb78c3d4 (diff)
target/arm: Use correct SP in M-profile exception return
When an M-profile CPU is restoring registers from the stack on exception return, the stack pointer to use is determined based on bits in the magic exception return type value. We were not getting this logic entirely correct. Whether we use one of the Secure stack pointers or one of the Non-Secure stack pointers depends on the EXCRET.S bit. However, whether we use the MSP or the PSP then depends on the SPSEL bit in either the CONTROL_S or CONTROL_NS register. We were incorrectly selecting MSP vs PSP based on the EXCRET.SPSEL bit. (In the pseudocode this is in the PopStack() function, which calls LookUpSp_with_security_mode() which in turn looks at the relevant CONTROL.SPSEL bit.) The buggy behaviour wasn't noticeable in most cases, because we write EXCRET.SPSEL to the CONTROL.SPSEL bit for the S/NS register selected by EXCRET.ES, so we only do the wrong thing when EXCRET.S and EXCRET.ES are different. This will happen when secure code takes a secure exception, which then tail-chains to a non-secure exception which finally returns to the original secure code. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210520130905.2049-1-peter.maydell@linaro.org
Diffstat (limited to 'accel')
0 files changed, 0 insertions, 0 deletions