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authorRichard Henderson <richard.henderson@linaro.org>2023-08-27 18:58:15 -0700
committerRichard Henderson <richard.henderson@linaro.org>2023-09-16 14:57:15 +0000
commit405c02d85de283dfe44560ae05db909d1f0cfd45 (patch)
treeca722efddd47d515afbcf0aa177b1f21973cad19 /accel
parent0e1144400fc390c0b6c37c252e95961cfab1dde9 (diff)
plugin: Simplify struct qemu_plugin_hwaddr
Rather than saving MemoryRegionSection and offset, save phys_addr and MemoryRegion. This matches up much closer with the plugin api. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'accel')
-rw-r--r--accel/tcg/cputlb.c16
1 files changed, 9 insertions, 7 deletions
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index a46be6a120..fd1b07c5a3 100644
--- a/accel/tcg/cputlb.c
+++ b/accel/tcg/cputlb.c
@@ -1724,23 +1724,25 @@ bool tlb_plugin_lookup(CPUState *cpu, vaddr addr, int mmu_idx,
uintptr_t index = tlb_index(env, mmu_idx, addr);
MMUAccessType access_type = is_store ? MMU_DATA_STORE : MMU_DATA_LOAD;
uint64_t tlb_addr = tlb_read_idx(tlbe, access_type);
+ CPUTLBEntryFull *full;
if (unlikely(!tlb_hit(tlb_addr, addr))) {
return false;
}
+ full = &env_tlb(env)->d[mmu_idx].fulltlb[index];
+ data->phys_addr = full->phys_addr | (addr & ~TARGET_PAGE_MASK);
+
/* We must have an iotlb entry for MMIO */
if (tlb_addr & TLB_MMIO) {
- CPUTLBEntryFull *full = &env_tlb(env)->d[mmu_idx].fulltlb[index];
- hwaddr xlat = full->xlat_section;
-
+ MemoryRegionSection *section =
+ iotlb_to_section(cpu, full->xlat_section & ~TARGET_PAGE_MASK,
+ full->attrs);
data->is_io = true;
- data->v.io.offset = (xlat & TARGET_PAGE_MASK) + addr;
- data->v.io.section =
- iotlb_to_section(cpu, xlat & ~TARGET_PAGE_MASK, full->attrs);
+ data->mr = section->mr;
} else {
data->is_io = false;
- data->v.ram.hostaddr = (void *)((uintptr_t)addr + tlbe->addend);
+ data->mr = NULL;
}
return true;
}