diff options
| author | Anton Johansson <anjo@rev.ng> | 2023-06-21 15:56:25 +0200 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2023-06-26 17:32:59 +0200 |
| commit | 9e39de980fdf0dbb083a5c78b71bf2c1bdfa0499 (patch) | |
| tree | cdad2a6ec643a307de6e440b3c67f051d4cf2089 /accel/tcg | |
| parent | bb5de52524c6c4b7da5623c5b19d9d6dc8405aa0 (diff) | |
accel/tcg/cputlb.c: Widen CPUTLBEntry access functions
Signed-off-by: Anton Johansson <anjo@rev.ng>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230621135633.1649-5-anjo@rev.ng>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'accel/tcg')
| -rw-r--r-- | accel/tcg/cputlb.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 5caeccb52d..ac990a1526 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1453,7 +1453,7 @@ static bool victim_tlb_hit(CPUArchState *env, size_t mmu_idx, size_t index, assert_cpu_is_self(env_cpu(env)); for (vidx = 0; vidx < CPU_VTLB_SIZE; ++vidx) { CPUTLBEntry *vtlb = &env_tlb(env)->d[mmu_idx].vtable[vidx]; - target_ulong cmp = tlb_read_idx(vtlb, access_type); + uint64_t cmp = tlb_read_idx(vtlb, access_type); if (cmp == page) { /* Found entry in victim tlb, swap tlb and iotlb. */ @@ -1507,7 +1507,7 @@ static int probe_access_internal(CPUArchState *env, target_ulong addr, { uintptr_t index = tlb_index(env, mmu_idx, addr); CPUTLBEntry *entry = tlb_entry(env, mmu_idx, addr); - target_ulong tlb_addr = tlb_read_idx(entry, access_type); + uint64_t tlb_addr = tlb_read_idx(entry, access_type); target_ulong page_addr = addr & TARGET_PAGE_MASK; int flags = TLB_FLAGS_MASK; @@ -1694,7 +1694,7 @@ bool tlb_plugin_lookup(CPUState *cpu, vaddr addr, int mmu_idx, CPUArchState *env = cpu->env_ptr; CPUTLBEntry *tlbe = tlb_entry(env, mmu_idx, addr); uintptr_t index = tlb_index(env, mmu_idx, addr); - vaddr tlb_addr = is_store ? tlb_addr_write(tlbe) : tlbe->addr_read; + uint64_t tlb_addr = is_store ? tlb_addr_write(tlbe) : tlbe->addr_read; if (likely(tlb_hit(tlb_addr, addr))) { /* We must have an iotlb entry for MMIO */ @@ -1759,7 +1759,7 @@ static bool mmu_lookup1(CPUArchState *env, MMULookupPageData *data, target_ulong addr = data->addr; uintptr_t index = tlb_index(env, mmu_idx, addr); CPUTLBEntry *entry = tlb_entry(env, mmu_idx, addr); - target_ulong tlb_addr = tlb_read_idx(entry, access_type); + uint64_t tlb_addr = tlb_read_idx(entry, access_type); bool maybe_resized = false; /* If the TLB entry is for a different page, reload and try again. */ |