diff options
author | Palmer Dabbelt <palmer@rivosinc.com> | 2022-03-30 09:59:13 -0700 |
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committer | Alistair Francis <alistair.francis@wdc.com> | 2022-04-01 08:40:42 +1000 |
commit | 5242ef887dd06659e3d516cb4000c8ed3277fb08 (patch) | |
tree | f4337ac60e09e86cec5699ad18edcabe87bbfbe0 /accel/meson.build | |
parent | d5341e09135b871199073572f53bc11ae9b44897 (diff) |
target/riscv: Avoid leaking "no translation" TLB entries
The ISA doesn't allow bare mappings to be cached, as the caches are
translations and bare mppings are not translated. We cache these
translations in QEMU in order to utilize the TLB code, but that leaks
out to the guest.
Suggested-by: phantom@zju.edu.cn # no name in the From field
Fixes: 1e0d985fa9 ("target/riscv: Only flush TLB if SATP.ASID changes")
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220330165913.8836-1-palmer@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'accel/meson.build')
0 files changed, 0 insertions, 0 deletions