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authorBlue Swirl <blauwirbel@gmail.com>2012-04-14 10:55:00 +0000
committerBlue Swirl <blauwirbel@gmail.com>2012-04-14 10:55:00 +0000
commite92861ccb166883b0672b1ddfebce4f5de85e23d (patch)
tree224d2b489985286be0afef1cd89ca5423ed5a9da /Makefile.target
parent7672725d41d1a04195affc1a7bd5676ba6314b14 (diff)
parentc79981ceec3ae1e712aa9c21cba94c152eea2fb5 (diff)
Merge branch 'arm-devs.for-upstream' of git://git.linaro.org/people/pmaydell/qemu-arm
* 'arm-devs.for-upstream' of git://git.linaro.org/people/pmaydell/qemu-arm: hw/arm_gic: Remove stray hardcoded tab hw/arm_gic: gic_set_pending_private() is NVIC only hw/arm_gic: Use NVIC instead of LEGACY_INCLUDED_GIC define hw/arm_gic: Make gic_reset a sysbus reset function hw/arm11mpcore: Convert to using sysbus GIC device hw/exynos4210_gic: Convert to using sysbus GIC hw/realview_gic: switch to sysbus GIC hw/a9mpcore: Switch to using sysbus GIC hw/a15mpcore: switch to using sysbus GIC hw/arm_gic: Make the GIC its own sysbus device hw/arm_gic: Expose PPI inputs as gpio inputs hw/arm_gic: Move gic_get_current_cpu into arm_gic.c hw/arm_gic: Move NCPU definition to arm_gic.c hw/exynos4210_combiner.c: Drop excessive read/write access check. ARM: Exynos4210: Drop gic_cpu_write() after initialization. Fix bit test in Exynos4210 UART emulation to use & instead of &&
Diffstat (limited to 'Makefile.target')
-rw-r--r--Makefile.target1
1 files changed, 1 insertions, 0 deletions
diff --git a/Makefile.target b/Makefile.target
index e88b896e38..8d2b2323c1 100644
--- a/Makefile.target
+++ b/Makefile.target
@@ -366,6 +366,7 @@ obj-arm-y += cadence_uart.o
obj-arm-y += cadence_ttc.o
obj-arm-y += cadence_gem.o
obj-arm-y += xilinx_zynq.o zynq_slcr.o
+obj-arm-y += arm_gic.o
obj-arm-y += realview_gic.o realview.o arm_sysctl.o arm11mpcore.o a9mpcore.o
obj-arm-y += exynos4210_gic.o exynos4210_combiner.o exynos4210.o
obj-arm-y += exynos4_boards.o exynos4210_uart.o exynos4210_pwm.o