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authorFabien Chouteau <chouteau@adacore.com>2019-02-12 18:38:39 +0100
committerPalmer Dabbelt <palmer@sifive.com>2019-05-24 11:58:30 -0700
commit30efbf330a45fc5b83457037927151adafc397ed (patch)
tree89111532c51d904f467ed1d879c239a775d5a43c /Makefile.objs
parenta7b21f6762a2d6ec08106d8a7ccb11829914523f (diff)
SiFive RISC-V GPIO Device
QEMU model of the GPIO device on the SiFive E300 series SOCs. The pins are not used by a board definition yet, however this implementation can already be used to trigger GPIO interrupts from the software by configuring a pin as both output and input. Signed-off-by: Fabien Chouteau <chouteau@adacore.com> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Diffstat (limited to 'Makefile.objs')
-rw-r--r--Makefile.objs1
1 files changed, 1 insertions, 0 deletions
diff --git a/Makefile.objs b/Makefile.objs
index d7491413c1..b61568ad06 100644
--- a/Makefile.objs
+++ b/Makefile.objs
@@ -182,6 +182,7 @@ trace-events-subdirs += hw/virtio
trace-events-subdirs += hw/watchdog
trace-events-subdirs += hw/xen
trace-events-subdirs += hw/gpio
+trace-events-subdirs += hw/riscv
trace-events-subdirs += migration
trace-events-subdirs += net
trace-events-subdirs += ui