diff options
| author | Peter Maydell <peter.maydell@linaro.org> | 2021-06-25 17:05:22 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2021-06-25 17:05:22 +0100 |
| commit | e3955ae93f5151ad2e982440b7c8d3776a9afee2 (patch) | |
| tree | 355a6ea83d17c09ba98cedbab0330e316d43e53d /MAINTAINERS | |
| parent | 3593b8e0a2146a885f93d71c754757bb2c03864e (diff) | |
| parent | 3ef6434409c575e11faf537ce50ca05426c78940 (diff) | |
Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-20210624-2' into staging
Third RISC-V PR for 6.1 release
- Fix MISA in the DisasContext
- Fix GDB CSR XML generation
- QOMify the SiFive UART
- Add support for the OpenTitan timer
# gpg: Signature made Thu 24 Jun 2021 13:00:26 BST
# gpg: using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054
# gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [full]
# Primary key fingerprint: F6C4 AC46 D493 4868 D3B8 CE8F 21E1 0D29 DF97 7054
* remotes/alistair/tags/pull-riscv-to-apply-20210624-2:
hw/riscv: OpenTitan: Connect the mtime and mtimecmp timer
hw/timer: Initial commit of Ibex Timer
hw/char/ibex_uart: Make the register layout private
hw/char: QOMify sifive_uart
hw/char: Consistent function names for sifive_uart
target/riscv: gdbstub: Fix dynamic CSR XML generation
target/riscv: Use target_ulong for the DisasContext misa
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'MAINTAINERS')
| -rw-r--r-- | MAINTAINERS | 6 |
1 files changed, 2 insertions, 4 deletions
diff --git a/MAINTAINERS b/MAINTAINERS index 3443d2a5b5..3ff56f53f9 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1365,11 +1365,9 @@ M: Alistair Francis <Alistair.Francis@wdc.com> L: qemu-riscv@nongnu.org S: Supported F: hw/riscv/opentitan.c -F: hw/char/ibex_uart.c -F: hw/intc/ibex_plic.c +F: hw/*/ibex_*.c F: include/hw/riscv/opentitan.h -F: include/hw/char/ibex_uart.h -F: include/hw/intc/ibex_plic.h +F: include/hw/*/ibex_*.h Microchip PolarFire SoC Icicle Kit M: Bin Meng <bin.meng@windriver.com> |