diff options
author | Peter Maydell <peter.maydell@linaro.org> | 2019-06-11 16:39:51 +0100 |
---|---|---|
committer | Peter Maydell <peter.maydell@linaro.org> | 2019-06-13 15:14:06 +0100 |
commit | b623d803dda805f07aadcbf098961fde27315c19 (patch) | |
tree | 0d265674ab44439f5b0a48acf0af224201e1b596 /LICENSE | |
parent | 386bba2368842fc74388a3c1651c6c0c0c70adbd (diff) |
target/arm: Convert the VCVT-from-f16 insns to decodetree
Convert the VCVTT, VCVTB instructions that deal with conversion
from half-precision floats to f32 or 64 to decodetree.
Since we're no longer constrained to the old decoder's style
using cpu_F0s and cpu_F0d we can perform a direct 16 bit
load of the right half of the input single-precision register
rather than loading the full 32 bits and then doing a
separate shift or sign-extension.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'LICENSE')
0 files changed, 0 insertions, 0 deletions